I am trying to create a half adder circuit using logisim to compute two 4 bit binary numbers but somehow Logisim tells me that I have incompatible widths and I therefore have to change the bit width of every single component including the carry-out which is suppose to be a 1 bit (showing carry 1 or carry 0). Now I understand that my output has to be at least 4 bit in length and I need an extra bit as a carry out but even when I change the length the way Logisim wants then my design does not work anymore.
Half adder of a 2 four bit binaries
It's simply because the input width on the AND gate is 1 bit. You can't have a 4-bit output going into a 1-bit input.
Related
I have a 32-bit number that is created by encoding some data, I want to be more confident that the data (a max 32-bit number) is not changed when decoding it, so I am going to add some error detection bits.
I need to keep the data as short as possible, so I can only add a few bits for error detection, in some cases just 1 bit.
I'm looking for an algorithm that detects more bit changes and needs fewer extra bits.
I was thinking of calculating a checksum or CRC and just dropping extra bits or maybe xor the result to make it shorter but I'm not sure if the error detection remains good enough.
Thanks in advance for any help.
A 1-bit CRC, with polynomial x+1 would simply be the parity of your 32 message bits. That will detect any one-bit error in the resulting 32 bits. For a 2-bit CRC, you can use x2+1. You can define a CRC of any length. See Koopman's list for good CRC polynomials for CRCs of degree 3 and higher.
Design a MultiplyByThree circuit using one 4-bit adder. A 4-bit adder is a circuit that performs the addition of two number consisting of 4 bits each. Additionally, you have a half adder, it is a circuit that performs the addition of two numbers consisting of one bit each. Assume that we have already manufactured 4-bit adder and half adder shown below.
I'm having trouble finding the answer to this using a theoretical 4-bit adder and one half adder. The only solution I could find was using 2 full-adders and 2 half-adders and even that I'm not sure of. The image below is my attempt at solving it using the conditions given in the question. Any help would be greatly appreciated.
enter image description here
and of course the equivalent syntax in VHDL?
Is the lower index a minimum bound for indexing? What happens in assignments between signals with differing bounds but the same width?
Assuming you meant the widths to be the same...
...so, in Verilog let's assume you meant
logic [19:4] v19_4;
logic [15:0] v15_0;
In a Verilog simulation, you will not experience any difference unless to try to index the bits.
If you index the bits, you will find that
in the first case, the left hand bit is bit 19 (ie v19_4[19]), whereas in the second case, the left hand bit is bit 15 (ie v15_0[15]);
in the first case, the right hand bit is bit 4 (ie v19_4[4]), whereas in the second case, the right hand bit is bit 0 (ie v15_0[0]).
In Verilog, it is valid to call the left hand bit "the MSB" and the right hand bit "the LSB".
You will experience exactly the same behaviour in VHDL. In VHDL let's assume you meant
signal v19_4 : std_logic_vector(19 downto 4);
signal v15_0 : std_logic_vector(15 downto 0);
Again, in a VHDL simulation, you will not experience any difference unless to try to index the bits. If you index the bits, you will find that
in the first case, the left hand bit is bit 19 (ie v19_4(19)), whereas in the second case, the left hand bit is bit 15 (ie v15_0(15));
in the first case, the right hand bit is bit 4 (ie v19_4(4)), whereas in the second case, the right hand bit is bit 0 (ie v15_0(0)).
With synthesis you might see a difference. It is generally recommended to index vectors from 0 for synthesis to remove the possibility of synthesising more bits than you need. However, I would think that most synthesisers would optimise away the excess logic.
I am trying to create a vhdl code that will randomly blink four LEDs. After pushing a button that corresponds to the blinking led, a score will be displayed using 7 segment after 60 seconds.
Can anyone help me in generating random LED blink for the 4 LEDs?
Have a look at a Linear Feedback Shift Register. That'll give you a pseudo-random sequence of whatever length you want, and it's both effective and easy to implement in VHDL.
Depending on "how random" you need your sequence to be, you could for instance create a 16 bit long LFSR, and then use four arbitrarily selected bits from this to display (instead of using four consecutive bits, which might make the next value easier to guess, depending on the implementation).
In two-complement to invert the sign of a number you usually just negate every bit and add 1.
For example:
011 (3)
100 + 1 = 101 (-3)
In VHDL is:
a <= std_logic_vector(unsigned(not(a)) + 1);
In this way the synthesizer uses an N-bit adder.
Is there another more efficient solution without using the adder?
I would guess there's not an easier way to do it, but the adder is probably not as bad as you think it is.
If you are trying to say invert a 32-bit number, the synthesis tool might start with a 32-bit adder structure. However then upon seeing that the B input is always tied to 1, it can 'hollow out' a lot of the structure due to the unused gates (AND gates with one pin tied to ground, OR gates with one pin tied to logic 1, etc).
So what you're left with I'd imagine would be a reasonably efficient blob of logic which just increments an input number.
If you are just trying to create a two's complement bit pattern then a unary - also works.
a = 3'b001 ; // 1
b = -a ; //3'b111 -1
c = ~a + 1 ; //3'b111 -1
Tim has also correctly pointed out that just because you use a + or imply one through a unary -, the synthesis tools are free to optimise this.
A full adder has 3 inputs (A, B, Carry_in) and 2 outputs (Sum Carry_out). Since for our use the second input is only 1 bit wide, and at the LSB there is no carry, we do not need a 'full adder'.
A half adder which has 2 inputs (A, B) and 2 outputs (Sum Carry), is perfect here.
For the LSB the half adders B input will be high, the +1. The rest of the bits B inputs will be used to propagate the Carry from the previous bit.
There is no way that I am aware of to write in verilog that you want a half adder, but any size number plus 1 bit only requires a half adder rather than a fulladder.