I use the Makefile to build the project.
After rebuild the project again without "make clean" before.
However, it takes a lot of time to rebuild it again.
It seems the syntax of the Makefile causing lots of time consuming.
But I am not familiar with Makefile syntax.
Could anyone points out the point if the statement incurs the lots of time
consuming of the Makefile.
Here is the Makefile that I use:
https://github.com/cokeco/Makefile/blob/master/Makefile
Use make -d output to debug why your targets are remade.
Related
I just took over a GCC project containing a makefile that has way to many include folders and source files listed. I started removing one by one and verified by compiling, but wondered, is there some way of looking at the compiled output (map files for instance?) and compare that to the makefile to clean out unnecessary files?
I'm not saying this will make any difference to the finished project, but I like to quickly look at the Makefile to see what this project involves. Now it looks like it involves "everything"
Using cmake 3.7.2 I recently switched a project from Unix Makefile to Cmake with Unix makefile generator.
All works as expected and the main problems we wanted to solve are solved (command line length in windows).
I discovered a great thing that is dependency checking as there is no more need to clean in normal situations and rebuild unneeded files.
Now the dependency is very slow (about 70s) when the all build is only 20s. Is there a way to speed up the checking ? Or to find the bottleneck of this check ?
GNU make dependency check IS slow.
Ninja was designed to be much faster ans IS definitely faster.
The update to Ninja is very simple as only cmake generator (-G) has to be modified.
This question already has an answer here:
how to make clean without any modification?
(1 answer)
Closed 3 years ago.
I have a very complicated makefile which I am not going to include here for obvious reasons. I have rules to build dependency files and then include them with lines along the lines of '-include myobj.d'.
I also (obviously) have a rule to build a *.d file.
I then have rules along the lines of
.PHONY: clean
clean:
rm myobj.d myobj.o ...
When I do make clean, first it rebuilds all the .d files before deleting them. I ran make with -d and examined the debug information and it is trying to rebuild all the files I include with "-include" before examining the targets it was told to build. I have a whole pile of "rules.mk" for building different code units and it tries to rebuild all of those too.
This wouldn't be a problem, except that the .d files that are being included actually do have rules to build them. When I say "make clean" I want make to just execute the clean rule, not rebuild all the stupid dependency files just so I can delete them...
This is particularly problematic if the build is in a weird state where half the code is built and the rest isn't and I am trying to do a make clean to get back to a good state.
How do I tell make to not try to automatically rebuild an included file?
You do not need rules for .d files these days, this is a common misconception. See Automatic header dependencies with gmake for more details.
I am currently working on a project on a student job and writing some code. Whenever I want to compile my file, my supervisor told me to first do gmake clean and then do gmake. Otherwise,some errors from previous gmake may not be solved in the fresh gmake.
My project has a lot of unnecessary files that I am not editing but since i gmake clean everytime, the compiler compiles them again everytime which takes a lot of time.
So, if I am not changing the other files, then I don't need to recompile them and the only file that I change is always recompiled simply with gmake, right? So why should I gmake clean everytime?
Is my supervisor just telling me a good programming practice or am I missing some important concept of gmake clean?
The difference between gmake and gmake clean is that the former builds the default target while the latter "builds" the specific target clean, which usually consists of clean-up instructions to remove files that were created during the build process (object files, temporary files, generated code, …). gmake clean should restore the source tree to a clean state. However, if it actually succeeds depends on how the source tree looks like and what instructions the target contains.
definitely not a best practice... this is usually the quick and dirty solution when the makefile contains a few mistakes and the dependencies are not ok
do gmake clean before gmake in case you have difficulties to compile. just to check if the problem does not come from an old compiled file.
otherise do only gmake in orther to compile your newest changed files.
you superior gived you an advice to handle difficult and strange compilation behavior.
A small change in a 1000's of lines of code leads to running the ./configure again on the entire software.
Is there any alternative, where we can compile only the changed file and the files associated with it?
If you have a sane Makefile.am with proper dependencies, running ./configure and make should only recompile files that depend on the touched file. So make already does what you are asking for.
If your Makefiles are not sane (e.g. they only work if you run make clean) and you are compiling C or C++ sources, using ccache might give you a speed gain. With ccache only the preprocessor part is run and its output compared to a cache of compile outputs. If nothing changed in the file or its includes it won't be recompiled. Properly installed it is run in a transparent way.