I just took over a GCC project containing a makefile that has way to many include folders and source files listed. I started removing one by one and verified by compiling, but wondered, is there some way of looking at the compiled output (map files for instance?) and compare that to the makefile to clean out unnecessary files?
I'm not saying this will make any difference to the finished project, but I like to quickly look at the Makefile to see what this project involves. Now it looks like it involves "everything"
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Maybe this has been asked before but I could not find anything, that answers my question precisely.
I created a New arm cortex cmsis cpp project in eclipse. This gave me the default folder structure. I build the debug config and now have the generated makefiles in the debug folder. From here I can Do "make clean" and "make and everything compiles fine. The makefiles (including the sub mk files) were to static for my needs, so I changed them to be more generic (I only tell the make where the src folders are and it scans all the folders for c and cpp files and builds All the obj files and dependencies). I also took the makefile out of the debug folder and put it one level up into the project folder. So all together, I changed the location of the makefile and made it more dynamic. Now when I run "make", everything runs fine. Everything is compiled BUT the generated .elf and .bin have a different size, compared to files, that were created with the original files. I can See in the terminal that make creates the same files in the same order with the same flags. Everything is identical except that the location of the files now is in ./ instead of ../ How is this possible?
Most object files and binaries contain information about the location of the source files, so that the debugger can locate them. There may be other changes such as date and time stamps (although it's unlikely this will change the size of the output).
You can run something like strings myprog | sort on both old and new programs and see if the strings in your program are now different sizes.
This question already has an answer here:
how to make clean without any modification?
(1 answer)
Closed 3 years ago.
I have a very complicated makefile which I am not going to include here for obvious reasons. I have rules to build dependency files and then include them with lines along the lines of '-include myobj.d'.
I also (obviously) have a rule to build a *.d file.
I then have rules along the lines of
.PHONY: clean
clean:
rm myobj.d myobj.o ...
When I do make clean, first it rebuilds all the .d files before deleting them. I ran make with -d and examined the debug information and it is trying to rebuild all the files I include with "-include" before examining the targets it was told to build. I have a whole pile of "rules.mk" for building different code units and it tries to rebuild all of those too.
This wouldn't be a problem, except that the .d files that are being included actually do have rules to build them. When I say "make clean" I want make to just execute the clean rule, not rebuild all the stupid dependency files just so I can delete them...
This is particularly problematic if the build is in a weird state where half the code is built and the rest isn't and I am trying to do a make clean to get back to a good state.
How do I tell make to not try to automatically rebuild an included file?
You do not need rules for .d files these days, this is a common misconception. See Automatic header dependencies with gmake for more details.
I'm working on my first project using cmake, and for the most part it's been going well but I've run into one problem I can't figure out.
Let's say I have my CMakeLists.txt file located at ~/project/build. I would like for the output from cmake (not the binaries, but the makefile/configuration files) to be independent of where I run cmake from.
As an example, if my terminal is sitting in the ~/project/build directory, calling cmake ~/project/build creates the makefile and everything else within the ~/project/build directory. This is the behaviour that I'd like. If I call cmake ~/project/build from anywhere else, it creates the makefile and everything else in whatever directory the terminal called the program from.
Is it possible to force cmake to generate its makefile and associated files in the same folder as the CMakeLists.txt file? I've taken a look through the documentation and I've had no problems figuring out how to change binary output directories, but I can't really find any mention of what I'm trying to do.
I realize this is a pretty minor annoyance (it's not that hard to move into my build folder before building the project) but I'm just wondering if it's possible and if there's some reason it wouldn't be advised.
You have to use 2 commands for this
1) cmake -B "Dest path(Any path in which u want to generate the output files)" -H"Source path(root CMakeLists.txt path)"
2) cmake --build "Dest path"
I am currently working on a project on a student job and writing some code. Whenever I want to compile my file, my supervisor told me to first do gmake clean and then do gmake. Otherwise,some errors from previous gmake may not be solved in the fresh gmake.
My project has a lot of unnecessary files that I am not editing but since i gmake clean everytime, the compiler compiles them again everytime which takes a lot of time.
So, if I am not changing the other files, then I don't need to recompile them and the only file that I change is always recompiled simply with gmake, right? So why should I gmake clean everytime?
Is my supervisor just telling me a good programming practice or am I missing some important concept of gmake clean?
The difference between gmake and gmake clean is that the former builds the default target while the latter "builds" the specific target clean, which usually consists of clean-up instructions to remove files that were created during the build process (object files, temporary files, generated code, …). gmake clean should restore the source tree to a clean state. However, if it actually succeeds depends on how the source tree looks like and what instructions the target contains.
definitely not a best practice... this is usually the quick and dirty solution when the makefile contains a few mistakes and the dependencies are not ok
do gmake clean before gmake in case you have difficulties to compile. just to check if the problem does not come from an old compiled file.
otherise do only gmake in orther to compile your newest changed files.
you superior gived you an advice to handle difficult and strange compilation behavior.
I am working on a system which is composed of many projects and makefiles. Each makefile includes .inc files from it`s dependencies. If a dependency is missing, it complains and tells the user to compile the dependency first. This part works ok. Problem is the clean target.
If a dependency is cleaned first and it`s inc file is deleted (since inc files include compile time options and hard paths, we prefer to delete them), then Makefile fails to load the .inc file and aborts. So the mechanism that makes sure we have the right dependencies, does not let us call the clean target -which does not require the dependencies-.
Is there any way to include or ignore .inc files according to the rule?
PS: Since we are already using "-" for error checking so that is not an option.
the canonical way to prevent including when cleaning is as follows:
ifneq ($(MAKECMDGOALS),clean)
include $(some .inc files)
endif
as described here https://www.gnu.org/software/make/manual/make.html#Goals
although if i understand correctly the errors you are experiencing are not because of the failed includes, which you are already supressing with -include, but because your makefile is dependent on some values from the includes.
to help you fix that we will need some code which demonstrates the problem. please read here for how to do so: https://stackoverflow.com/help/minimal-reproducible-example and http://www.sscce.org/