Make rebuilds files included with -include [duplicate] - makefile

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how to make clean without any modification?
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Closed 3 years ago.
I have a very complicated makefile which I am not going to include here for obvious reasons. I have rules to build dependency files and then include them with lines along the lines of '-include myobj.d'.
I also (obviously) have a rule to build a *.d file.
I then have rules along the lines of
.PHONY: clean
clean:
rm myobj.d myobj.o ...
When I do make clean, first it rebuilds all the .d files before deleting them. I ran make with -d and examined the debug information and it is trying to rebuild all the files I include with "-include" before examining the targets it was told to build. I have a whole pile of "rules.mk" for building different code units and it tries to rebuild all of those too.
This wouldn't be a problem, except that the .d files that are being included actually do have rules to build them. When I say "make clean" I want make to just execute the clean rule, not rebuild all the stupid dependency files just so I can delete them...
This is particularly problematic if the build is in a weird state where half the code is built and the rest isn't and I am trying to do a make clean to get back to a good state.
How do I tell make to not try to automatically rebuild an included file?

You do not need rules for .d files these days, this is a common misconception. See Automatic header dependencies with gmake for more details.

Related

Is there better way to build one cpp which is in Makefile project?

I have one huge makefile-based project.
I download it from git and modify some .cpp files.
I want to just build those files I modifyed.
Now I think I can use make -n |grep > build.sh then run the build.sh.
Is there better way ? Thanks.
Without any information about how your makefile works there's not much definitive we can say.
If you just want to rebuild foo.cpp, you should be able to run make foo.o. But of course, this depends on how complex your makefiles are, whether they're recursive, whether they build the object file in a different directory, etc.

How to clean up a GCC Makefile

I just took over a GCC project containing a makefile that has way to many include folders and source files listed. I started removing one by one and verified by compiling, but wondered, is there some way of looking at the compiled output (map files for instance?) and compare that to the makefile to clean out unnecessary files?
I'm not saying this will make any difference to the finished project, but I like to quickly look at the Makefile to see what this project involves. Now it looks like it involves "everything"

[CMAKE]: Can't remove the .d and .gcno files generated by cmake using make clean command

I am building my project with cmake. I am able to generate the Makefiles on linux platform and hence able to build the project as well.
However, When I want to clean the all generated files, I am not able to do so.
I am not able to remove the foo.c.gcno and foo.c.d kind of files, using make clean command.
Is there any specific command in cmake to remove these intermediate files ?
Note: I have different directories for Cmake-source and build. I am concerned about the generated files(*.c.gcno and *.d) in the build directory. Rest all other files like *.o and *.so are cleaned up by make clean command.
In CMake, you cannot generate a Makefile and delete the rest. All the generated files, and an installed CMake, is still needed to build the project.
You should have run cmake <source directory> in a different directory in the first place. Let's call it build directory.
Then, build directory can be completely removed without changing the source code.

Difference Between 'gmake' and 'gmake clean'

I am currently working on a project on a student job and writing some code. Whenever I want to compile my file, my supervisor told me to first do gmake clean and then do gmake. Otherwise,some errors from previous gmake may not be solved in the fresh gmake.
My project has a lot of unnecessary files that I am not editing but since i gmake clean everytime, the compiler compiles them again everytime which takes a lot of time.
So, if I am not changing the other files, then I don't need to recompile them and the only file that I change is always recompiled simply with gmake, right? So why should I gmake clean everytime?
Is my supervisor just telling me a good programming practice or am I missing some important concept of gmake clean?
The difference between gmake and gmake clean is that the former builds the default target while the latter "builds" the specific target clean, which usually consists of clean-up instructions to remove files that were created during the build process (object files, temporary files, generated code, …). gmake clean should restore the source tree to a clean state. However, if it actually succeeds depends on how the source tree looks like and what instructions the target contains.
definitely not a best practice... this is usually the quick and dirty solution when the makefile contains a few mistakes and the dependencies are not ok
do gmake clean before gmake in case you have difficulties to compile. just to check if the problem does not come from an old compiled file.
otherise do only gmake in orther to compile your newest changed files.
you superior gived you an advice to handle difficult and strange compilation behavior.

gnu make, include and clean target

I am working on a system which is composed of many projects and makefiles. Each makefile includes .inc files from it`s dependencies. If a dependency is missing, it complains and tells the user to compile the dependency first. This part works ok. Problem is the clean target.
If a dependency is cleaned first and it`s inc file is deleted (since inc files include compile time options and hard paths, we prefer to delete them), then Makefile fails to load the .inc file and aborts. So the mechanism that makes sure we have the right dependencies, does not let us call the clean target -which does not require the dependencies-.
Is there any way to include or ignore .inc files according to the rule?
PS: Since we are already using "-" for error checking so that is not an option.
the canonical way to prevent including when cleaning is as follows:
ifneq ($(MAKECMDGOALS),clean)
include $(some .inc files)
endif
as described here https://www.gnu.org/software/make/manual/make.html#Goals
although if i understand correctly the errors you are experiencing are not because of the failed includes, which you are already supressing with -include, but because your makefile is dependent on some values from the includes.
to help you fix that we will need some code which demonstrates the problem. please read here for how to do so: https://stackoverflow.com/help/minimal-reproducible-example and http://www.sscce.org/

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