I am following the solution in GNU Makefile treating each recipe line as sub-shell command without continuation character
target_compile: PROJECT_SIM_OPTS += -LDFLAGS -L${CURRENT_DIR},-lm -load
target_compile: copy_shared_object actual_compile_with_sim_opts
#echo PROJECT_SIM_OPTS=${PROJECT_SIM_OPTS} ...
When I make the Makefile, I am able to see the second target_compile fire off but not the first target_compile which has no dependencies and recipe except a variable. I tried adding override before PROJECT_SIM_OPTS and ; at the end of the line but still it is not working.
There is no Error message reported which makes it even harder to detect. In nutshell, I have to embed this piece of code in another Makefile and if the first target would work, I will see a file generated with -LDFLAGS -L${CURRENT_DIR},-lm -load in it. Since this file is being generated without these flags, I am confident to say that first target is not firing.
How can the two target_compile work together?
It turned out to be an ordering issue. In my case
target_compile: copy_shared_object actual_compile_with_sim_opts
#echo PROJECT_SIM_OPTS=${PROJECT_SIM_OPTS} ...
actual_compile_with_sim_opts was running before copy_shared_object
Once I put the dependency like this,
actual_compile_with_sim_opts: copy_shared_object
I was able to get both targets to work with proper flags
Thanks #Beta for all the help.
Related
DEPRECATED_CHECK := $(shell grep "test454" tex/*.tex)
ifneq ($(DEPRECATED_CHECK), )
$(warning \test454 is deprecated. Use \test2 instead)
endif
When I run this I get:
../common/Makefile.include:133: \test454 is deprecated. Use \test2 instead
That's fine, but I'd quite like to have only:
\test454 is deprecated. Use \test2 instead
Is this possible? Some sort of awk function? I think I need something with:
#echo \text454 is deprecated ...
But I don't know how to get this working with the basic purpose of my MWE, as it keeps complaining about missing separators.
Many thanks
You could use $(info ...) instead of $(warning ...). info doesn't prepend the file and line number.
just an aside -- I usually try to do those sort of checks as part of a sanity rule, and make everything depend on that rule instead of doing it at the top level. It gives you more flexibility that way. For example, if you didn't want to run the check when building clean, it becomes simple, or if you wanted to fail the build if a check failed, it becomes simple as well.
EDIT (adding more detail on aside)
Instead of doing an ifneq at the top level of make, you could add a target as so:
sanity_check:
# ! grep -q "test454" tex/*.txt || echo "test454 is depricated"
.PHONY: sanity check
The add dependencies of your main targets to sanity check:
all maintarg1 maintarg2: sanity_check
This way the sanity check will be run before any of your main targets, and will output as desired. This is in my opinion, a cleaner way of doing the test. This way the test is only run if you are building any of your targets, and will not be run, if for example you are making clean, or if your makefile was included by a parent makefile, or in a bunch of other corner cases that might pop up in the future.
Just a quick note on the recipe syntax: the # is a make directive that tells make not to echo the command as it's run. The ! is bash syntax to inverse the return of grep (so ! grep returns false if the text is found, thereby causing the || part of the statement to be evaluated.). The .PHONY: sanity_check tells make to run the rule, even if a file called sanity_check already exists
I want to have a generic Makefile that takes any target name and for that target name, checks to see if certain sources exist and then executes some commands. So for example I want to be able to enter:
make mytarget
then make should check to see if mytarget.src1 and mytarget.src2 exist, and if so execute some commands.
I have the following makefile:
%:
$(MYCOMMANDS) $*.scr1 $*.scr2
the only problem with this is that it doesn't check to see if $.scr1 and $.scr2 exist before running $(MYCOMMANDS). This is understandable because I haven't specified any dependencies. However when I try:
%: $*.src1 $*.src2
$(MYCOMMANDS) $*.scr1 $*.scr2
it now doesn't ever run $(MYCOMMAND) and says no rule to make the specified target.
Can someone please explain why in my second code make cannot find the target? Also, how can I achieve the behavior that I want?
The correct way to write a pattern rule is to use the pattern (%) in both the target and the prerequisites:
%: %.src1 %.src2
$(MYCOMMANDS) $^
See Pattern Rules in the GNU make manual. Also see Automatic Variables. By the way, the third paragraph in the second link will explain why your second attempt, using $* in the prerequisites, cannot work.
I was able to get the behavior I want using the MAKECMDGOALS variable. So:
$(MAKECMDGOALS): $(MAKECMDGOALS).src1 $(MAKECMDGOALS).src2
$(MYCOMMANDS) $(MAKECMDGOALS).scr1 $(MAKECMDGOALS).scr2
does what I am looking for. It checks to make sure .src1 and .src2 exist. If they don't make will report an error and if they do it will run $(MYCOMMANDS).
In a makefile I use there is #-, that is not mentioned in any makefile tutorial I could find.. Could you please explain what #- is for?
For example:
#- $(RM) *.o
The at-sign # tells Make to not print the command line before executing it.
(Manual: Recipe echoing)
The minus sign - tells Make to ignore the result of the command and not fail the target if it was unsuccessful.
(Manual: Errors in recipes)
In your case it's just both of them being used, because somebody did not want to pollute the output with the erase command, and did not want to fail the build if anything goes wrong with the deletion either.
I created a Makefile.in where I read the content out of a file and pass it to CFLAGS. Calling ./configure ... the Makefile will be generated an all works well.
Makefile.in:
...
MY_REVISION_FILE=my-revision.txt
MY_REVISION=$(shell cat $(top_srcdir)/$(MY_REVISION_FILE))
AM_CFLAGS = -I$(EXTRAS_INCLUDE_DIR) -I$(top_srcdir) -DMY_REVISION=$(MY_REVISION)
...
The problem arises once I moved the Makefile.in code into Makefile.am to allow the auto generation of Makefile.in. There calling autoreconf -i --force stops with the following error:
server/Makefile.am:9: cat $(top_srcdir: non-POSIX variable name
server/Makefile.am:9: (probably a GNU make extension)
autoreconf: automake failed with exit status: 1
This problem hunts me now since quite some time. I searched everywhere but did not find anything that could help me finding a solution for that. In short, the only thing I need is a way to get an uninterpreted text such as "$(shell cat $(top_srcdir)/$(MY_REVISION_FILE))" copied from Makefile.am to Makefile.in
Any idea?
Thanks,
Oliver
As it says, the problem is you're using a GNUism in your Makefile.am, when it's only meant to contain portable Makefile code.
Either rewrite your code so it's portable (you should use AM_CPPFLAGS because you're passing flags to the preprocessor, not the compiler):
AM_CPPFLAGS = -I$(EXTRAS_INCLUDE_DIR) -I$(top_srcdir) -DMY_REVISION=`cat $(top_srcdir)/$(MY_REVISION_FILE)`
If you don't want to invoke cat on every compile, you could find the value in configure.ac and either AC_SUBST it into Makefile or AC_DEFINE it so it goes into config.h.
Or if you want to be non-portable (ಠ_ಠ), you can take -Werror out of your AM_INIT_AUTOMAKE or AUTOMAKE_OPTIONS, or add -Wno-portability.
After long testing back and forth I decided to use AC_SUBST.
My solution might not be the cleanest but it works for me.
In configure.ac I added the following line
AC_SUBST([DOLLAR_SIGN],[$])
In the Makefile.am I changed my previous line into
MY_REVISION=#DOLLAR_SIGN#(shell cat $(SRC_DIR)/$(MY_REVISION_FILE))
And it works.
Again, thanks for your help.
Part of my Makefile:
CPUDEPS=./mydeps.cpu
(...)
deps: $(CPUDEPS)
$(CPUDEPS): $(CCFILES)
#echo [DEPS] CPU
$(CMDECHO)makedepend -Y -s'# CPU sources dependencies generated with "make deps"' \
-w4096 -f- -- $(CFLAGS) -- $^ 2> /dev/null > $(CPUDEPS)
(...)
sinclude $(CPUDEPS)
Problem 1: includes are done during the first phase of processing, targets during the second phase; so, if ./mydeps.cpu doesn't exist and I "make deps", I get first the error
Makefile:335: ./mydeps.cpu: No such file or directory
I hide the error using sinclude instead of include, but the problem is still there: the old file is included, not the just-generated-one. Have to run it twice to include the updated file. This is because make does a two-phase processing; is there any way to tell make to complete the target deps before parsing the includes?
Problem 2: even if the file ./mydeps.cpu doesn't exist and make deps actually creates it, I always get a "make: Nothing to do for deps". This doesn't happen with other targets. I don't understand why and how to avoid it.
Problem 1 is non-existant: before building a target, make automatically rebuilds makefiles (with implicit rules if no explicit rule is provided). So having a rule for the makefile ensures that will always be up to date, there is no need to run deps twice. Additionally, since CPUDEPS is a makefile, it will be updated automatically before any other rule is run, so dependencies will always be updated if necessary and make deps is not needed. You can probably notice this by yourself by observing the [DEPS] line being echoed if any of the CCFILES becomes more recent that the dependency file.
For Problem 2, adding anything to the recipe ensures that make doesn't complain about having nothing to do. If there is nothing else, you can use something like #echo OK to give feedback to the user, or a simple #true if you prefer totally silent makes.
What you are trying to achieve is useless: you can use the dependencies file that was created during the previous build. That's enough.
The main reasoning behind that rule is:
if you haven't changed any of your files, then the dependencies file is up-to-date, and there's nothing to build.
if you have changed anything, even very deep into your #include chain, on an existing file that were used by previous build, then the dependencies file have already caught it. You'll rebuild what is needed.
if you change something in a new file (you add that file!) then it was not used by previous build, and not listed in dependencies. But if you really want to use it, then you have to modify at least one of your other files that was used before, and you're back on the previous case.
The solution is to create the dependencies file during the normal process of the compilation, and to optionally include it (with sinclude) if it is present.