I am trying to implement counter which gives as output values from one to six, which I want to later put on 7 segment display on fpga. The problem is with CLK, process doesn't see value of CLK changing and simulation gives as output always set of values "1001111".
library ieee;
use ieee.std_logic_1164.all;
entity projekt is
generic ( half_period : time := 10ms);
port(Q : out std_logic_vector(6 downto 0));
end projekt;
architecture a1 of projekt is
signal CLK : std_logic := '0';
begin
CLK <= not CLK after half_period;
process(CLK)
variable tmpQ : integer range 0 to 7 := 1;
begin
if ( CLK = '1' and CLK'event ) then
tmpQ := tmpQ + 1;
if tmpQ = 7 then
tmpQ := 1;
end if;
end if;
case tmpQ is
when 1 => Q <= "1001111";
when 2 => Q <= "0010010";
when 3 => Q <= "0000110";
when 4 => Q <= "1001100";
when 5 => Q <= "0100100";
when 6 => Q <= "0100000";
when others => Q <= "1111111";
end case;
end process;
end a1;
Is it CLK not changing or program never enters if statement?
Related
I am literally writing this in desperation. i've tried some many times to make it work and it just doesn't.
im using Altera DE2 board - Cyclone II EP2C35F672C6 & been trying to display simple image on 640x480 vga screen.
im using a vga controller design i made for a different board- Altera DE1 which worked really good.
the difference on this DE2 board is a different DAC component which has 10bit rgb data instead of 4bit like in the DE1 board, and it has extra needed ouputs - VGA_SYNC, VGA_BLANK, VGA_CLK.
So i made the needed changes & found an example where it says to set VGA_BLANK to '1' constant and VGA_SYNC to '0'. VGA_CLK is connected to the 25.175 Mhz pixel clk which is the pll clk output.
i've tried so many variations & tried to use another example where they set vga_blank to '1' when in visable aread & '0' when not and it still didnt work. i just get a black screen saying no video input when i run the design.
below is the implementation of my timing generator, data_generator & vga_top_level
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.vga_consts.all;
entity vga_toplevel is
port
(
-- in --
clk, rst : in std_logic;
-- out --
vga_clk, vga_blank, vga_sync : out std_logic;
r_data, g_data, b_data : out std_logic_vector(9 downto 0);
h_sync, v_sync : out std_logic
);
end entity;
architecture structural of vga_toplevel is
component pll
port
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
component timing_generator
port
(
clk, rst : in std_logic;
h_cnt : out integer range 0 to h_frame-1;
v_cnt : out integer range 0 to v_frame-1;
vga_blank, vga_sync : out std_logic;
h_sync, v_sync : out std_logic
);
end component;
component data_generator
generic
(
vis_x : integer := visable_x;
vis_y : integer := visable_y
);
port
(
clk, rst : in std_logic;
h_cnt : in integer range 0 to h_frame-1;
v_cnt : in integer range 0 to v_frame-1;
-- RGB values
r_data, g_data, b_data : out std_logic_vector(9 downto 0)
);
end component;
signal h_cnt, v_cnt : integer range 0 to h_frame-1;
signal pll_clk, rst_out, locked : std_logic;
-------------------------------------------------------------------
begin
rst_out <= not locked; -- uncomment for PLL use
vga_clk <= pll_clk;
-- rst_out <= rst; -- comment for PLL use
-- pll_clk <= clk; -- comment for PLL use
PLL1: pll
port map
(
inclk0 => clk,
areset => rst,
c0 => pll_clk,
locked => locked
);
T_GEN: timing_generator
port map
(
-- in --
clk => pll_clk,
rst => rst_out,
-- out --
vga_blank => vga_blank,
vga_sync => vga_sync,
v_cnt => v_cnt,
h_cnt => h_cnt,
v_sync => v_sync,
h_sync => h_sync
);
D_GEN: data_generator
port map
(
-- in --
clk => pll_clk,
rst => rst_out,
v_cnt => v_cnt,
h_cnt => h_cnt,
r_data => r_data,
g_data => g_data,
b_data => b_data
);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.vga_consts.all;
entity timing_generator is
port
(
clk, rst : in std_logic;
h_cnt : out integer range 0 to h_frame-1;
v_cnt : out integer range 0 to v_frame-1;
vga_blank : out std_logic;
vga_sync : out std_logic;
h_sync, v_sync : out std_logic
);
end entity;
architecture behave of timing_generator is
signal h_cnt_inner : integer range 0 to h_frame-1;
signal v_cnt_inner : integer range 0 to v_frame-1;
begin
vga_blank <= '1';
vga_sync <= '0';
h_cnt <= h_cnt_inner;
v_cnt <= v_cnt_inner;
-- counter for pixels --
process (clk, rst)
begin
if rst = '1' then
h_cnt_inner <= 0;
elsif rising_edge(clk) then
if h_cnt_inner = h_frame-1 then
h_cnt_inner <= 0;
else
h_cnt_inner <= h_cnt_inner + 1;
end if;
end if;
end process;
-- counter for lines --
process (clk, rst)
begin
if rst = '1' then
v_cnt_inner <= 0;
elsif rising_edge(clk) then
if v_cnt_inner = v_frame-1 then
v_cnt_inner <= 0;
elsif h_cnt_inner = 654 then
v_cnt_inner <= v_cnt_inner + 1;
end if;
end if;
end process;
-- h_sync generator --
process (clk, rst)
begin
if rst = '1' then
h_sync <= '1';
elsif rising_edge(clk) then
if h_cnt_inner = h_sync_d(0)-1 then
h_sync <= '0';
elsif h_cnt_inner = h_sync_d(1) then
h_sync <= '1';
end if;
end if;
end process;
-- v_sync generator --
process(clk, rst)
begin
if rst = '1' then
v_sync <= '1';
elsif rising_edge(clk) then
if v_cnt_inner = v_sync_d(0) then
v_sync <= '0';
elsif v_cnt_inner = v_sync_d(1) + 1 then
v_sync <= '1';
end if;
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.vga_consts.all;
entity data_generator is
generic (
vis_x : integer := visable_x;
vis_y : integer := visable_y
);
port
(
clk, rst : in std_logic;
h_cnt : in integer range 0 to h_frame-1;
v_cnt : in integer range 0 to v_frame-1;
-- RGB values for each pixel
r_data, g_data, b_data : out std_logic_vector(9 downto 0)
);
end entity;
architecture behave of data_generator is
begin
-- process to handle only 1 color - blue screen
process(clk, rst)
begin
if rst = '1' then
r_data <= (others => '0');
g_data <= (others => '0');
b_data <= (others => '0');
elsif rising_edge(clk) then
if (h_cnt >= h_vis_d(0)) and (h_cnt < h_vis_d(1)) and (v_cnt >= v_vis_d(0)) and (v_cnt < v_vis_d(1)) then
-- if in visiable area
r_data <= (others => '1');
g_data <= (others => '1');
b_data <= (others => '1');
else
r_data <= (others => '0');
g_data <= (others => '0');
b_data <= (others => '0');
end if;
end if;
end process;
end architecture;
I have to do UART with vhdl on the Xilinx which will send 16 chars string. I wrote such code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.ALL;
entity uartByJackob is
Port ( CLK, A, B, C : in STD_LOGIC;
RESET : in STD_LOGIC;
TxD, TxDOSC : out STD_LOGIC);
end uartByJackob;
architecture Behavioral of uartByJackob is
signal K: std_logic_vector(14 downto 0);
signal Q: std_logic_vector(3 downto 0);
signal CLK_Txd: std_logic;
signal ENABLE: std_logic;
signal QTxD: std_logic_vector(9 downto 0);
signal DATA : STD_LOGIC_VECTOR(7 downto 0);
-- freq of clock
begin
process(CLK, RESET)
begin
if rising_edge(CLK) then
if(A = '1' and K < 10416) then
K <= K + 1;
CLK_Txd <= K(13);
elsif(B = '1' and K < 5208) then
K <= K + 1;
CLK_Txd <= K(12);
elsif(C = '1' and K < 20832) then
K <= K + 1;
CLK_Txd <= K(14);
else
K <= (others => '0');
end if;
end if;
end process;
--counter
process(CLK_Txd, RESET, ENABLE)
begin
if(RESET = '1' and ENABLE = '0') then
Q <= "0000";
elsif (rising_edge(CLK_Txd)) then
Q <= Q + 1;
end if;
end process;
--comparator
ENABLE <= '1' when (Q > 4) else '0';
--transcoder
process(Q, CLK_Txd)
begin
if (rising_edge(CLK_Txd)) then
case Q is
when "0001" => DATA <= x"40";
when "0010" => DATA <= x"41";
when "0011" => DATA <= x"42";
when "0100" => DATA <= x"43";
when "0101" => DATA <= x"44";
when "0110" => DATA <= x"45";
when "0111" => DATA <= x"46";
when "1000" => DATA <= x"47";
when "1001" => DATA <= x"48";
when "1010" => DATA <= x"49";
when "1011" => DATA <= x"50";
when "1100" => DATA <= x"51";
when "1101" => DATA <= x"52";
when "1110" => DATA <= x"53";
when "1111" => DATA <= x"54";
when others => DATA <= x"55";
end case;
end if;
end process;
--uart
process(CLK_Txd, ENABLE, DATA)
begin
if(ENABLE = '0') then
QTxD <= DATA & "01";
elsif rising_edge(CLK_Txd) then
QTxD <= '1'&QTxD(9 downto 1);
end if;
end process;
TxD <= QTxD(0);
TxDOSC <= QTxD(0);
end Behavioral;
It's send data completely not connected with that what i have in transcoder and realy dont know why. Do you have any ideas what is wrong with my code, or do you have any diffrent examples of it how to send your own 16 chars with uart? I suppose that something is wrong with my counter or comparator.
--EDIT
Thans for your effort, i can't try your code at the Xilinx right now couse I am workin on it at my university. I see that you made a lot of changes in my code. Of course first i try to do it like you show and i hope this will be acceptable, but I propably have to do it with transcoder according to this picture.
From last time i made such changes i my code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.ALL;
entity uartByJackob is
Port ( CLK, A, B, C : in STD_LOGIC;
RESET : in STD_LOGIC;
TxD, TxDOSC : out STD_LOGIC);
end uartByJackob;
architecture Behavioral of uartByJackob is
signal K: std_logic_vector(14 downto 0);
signal Q: std_logic_vector(7 downto 0);
signal CLK_Txd: std_logic;
signal ENABLE: std_logic;
signal QTxD: std_logic_vector(7 downto 0);
signal DATA : STD_LOGIC_VECTOR(7 downto 0);
signal QPrim: std_logic_vector(3 downto 0);
begin
process(CLK, RESET)
begin
CLK_Txd <= CLK;
end process;
process(CLK_Txd, RESET, ENABLE)
begin
if(ENABLE = '0') then
Q <= "00000000";
elsif (rising_edge(CLK_Txd)) then
Q <= Q + 1;
end if;
end process;
ENABLE <= '1' when (Q <= 255) else '0';
process(Q(7 downto 4))
begin
case Q(7 downto 4) is
when "0000" => DATA <= x"40";
when "0001" => DATA <= x"41";
when "0010" => DATA <= x"42";
when "0011" => DATA <= x"43";
when "0100" => DATA <= x"44";
when "0101" => DATA <= x"45";
when "0110" => DATA <= x"46";
when "0111" => DATA <= x"47";
when "1000" => DATA <= x"48";
when "1001" => DATA <= x"49";
when "1010" => DATA <= x"50";
when "1011" => DATA <= x"51";
when "1100" => DATA <= x"52";
when "1101" => DATA <= x"53";
when "1110" => DATA <= x"54";
when "1111" => DATA <= x"55";
when others => DATA <= x"56";
end case;
end process;
process(CLK_Txd, ENABLE, DATA)
begin
if(ENABLE = '1') then
QTxD <= DATA;
elsif rising_edge(CLK_Txd) then
QTxD <= '1'&QTxD(7 downto 1);
end if;
end process;
TxD <= QTxD(0);
TxDOSC <= QTxD(0);
end Behavioral;
According to that i send MSB to transcoder and LSB to comparator but my program all the time still send x"40" to DATA and it is propably connected with this counter which you were talking about.
There is my simulation efect. I becoming upset with that couse i don't have enough skills in vhdl to do it by my self. I hope that you will help me to do rebuild my project. On simulation it looks good i dont know how it looks on Xilinx.
Can you show me a piece of code? - Stefan
The entire purpose to providing the link to Adrian Adamcyzk's code (Altera FPGA hardware (has an issue) vs ModelSim simulation (ok) - self implemented UART) was to provide an example with a bit (baud) counter and flip flop used to control sending the message once.
Here's Jackob's modified:
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity uartbyjackob is
port (
clk, a, b, c: in std_logic;
reset: in std_logic;
txd, txdosc: out std_logic
);
end entity uartbyjackob;
architecture foo of uartbyjackob is
-- signal k: unsigned(14 downto 0); -- FOR simulation
-- note if k were used in simulation it would require initialization
signal q: unsigned (3 downto 0); -- WAS std_logic_vector
signal clk_txd: std_logic;
signal enable: std_logic;
signal qtxd: std_logic_vector(9 downto 0);
-- signal data: std_logic_vector(7 downto 0);
-- added:
signal bdcnt: unsigned (3 downto 0);
signal ldqtxd: std_logic;
signal davl: std_logic;
type data_lut is array (0 to 15) of std_logic_vector (7 downto 0);
constant data: data_lut := (
x"40", x"41", x"42", x"43", x"44", x"45", x"46", x"47",
x"48", x"49", x"50", X"51", x"52", X"53", x"54", x"55"
);
signal datalut: std_logic_vector (7 downto 0); -- FOR SIMULATION visibility
begin
-- -- freq of clock -- NOTE k never in known binary state for simulation
-- process (clk, reset)
-- begin
-- if rising_edge(clk) then
-- if a = '1' and k < 10416 then
-- k <= k + 1;
-- clk_txd <= k(13);
-- elsif b = '1' and k < 5208 then
-- k <= k + 1;
-- clk_txd <= k(12);
-- elsif c = '1' and k < 20832 then
-- k <= k + 1;
-- clk_txd <= k(14);
-- else
-- k <= (others => '0');
-- end if;
-- end if;
-- end process;
clk_txd <= clk; -- SHORTENS SIMULATION
DAVL_FF: -- DATA_AVAILABLE to send
process (clk_txd, reset)
begin
if reset = '1' then
davl <= '0';
elsif rising_edge (clk_txd) then
if q = 15 and bdcnt = 9 then -- a JK FF equivalent
davl <= '0';
elsif q = 0 then
davl <= '1'; -- one clock holderover from reset
-- else
-- davl <= davl;
end if;
end if;
end process;
-- process(clk_txd, reset, enable)
-- begin
-- if reset = '1' and enable = '0' then
-- q <= "0000";
-- elsif rising_edge(clk_txd) then
-- q <= q + 1;
-- end if;
-- end process;
QCNT:
process (clk_txd, reset)
begin
if reset = '1' then
q <= (others => '0');
elsif rising_edge (clk_txd) then
if enable = '1' then
q <= q + 1;
end if;
end if;
end process;
BAUD_COUNTER:
process (clk_txd, reset)
begin
if reset = '1' then
bdcnt <= (others => '0');
elsif rising_edge (clk_txd) then
if davl = '0' or bdcnt = 9 then
bdcnt <= (others => '0');
else
bdcnt <= bdcnt + 1;
end if;
end if;
end process;
-- comparator
-- enable <= '1' when (q > 4) else '0';
enable <= '1' when bdcnt = 9 and davl = '1' and q /= 15 else
'0';
-- q latches at 15;
ldqtxd <= '1' when bdcnt = 9 and davl = '1' else
'0';
datalut <= data(to_integer(q)); -- FOR SIMULATION VISIBILITIY
--transcoder
-- process(q, clk_txd)
-- begin
-- if rising_edge(clk_txd) then
-- case q is
-- when "0001" => data <= x"40";
-- when "0010" => data <= x"41";
-- when "0011" => data <= x"42";
-- when "0100" => data <= x"43";
-- when "0101" => data <= x"44";
-- when "0110" => data <= x"45";
-- when "0111" => data <= x"46";
-- when "1000" => data <= x"47";
-- when "1001" => data <= x"48";
-- when "1010" => data <= x"49";
-- when "1011" => data <= x"50";
-- when "1100" => data <= x"51";
-- when "1101" => data <= x"52";
-- when "1110" => data <= x"53";
-- when "1111" => data <= x"54";
-- when others => data <= x"55";
-- end case;
-- end if;
-- end process;
-- uart
-- process (clk_txd, enable, data)
-- begin
-- if enable = '0' then
-- qtxd <= data & "01";
-- elsif rising_edge(clk_txd) then
-- qtxd <= '1' & qtxd(9 downto 1);
-- end if;
-- end process;
TX_SHIFT_REG:
process (clk_txd, reset) -- shift regiseter Tx UART
begin
if reset = '1' then
qtxd <= (others => '1'); -- output mark by default
elsif rising_edge (clk_txd) then
if ldqtxd = '1' then
qtxd <= '1' & data(to_integer(q)) & '0';
-- STOP & Data(q) 7 downto 0 & START , a MUX and expansion
else
qtxd <= '1' & qtxd(9 downto 1); -- shift out;
end if;
end if;
end process;
txd <= qtxd(0);
txdosc <= qtxd(0);
end architecture foo;
library ieee;
use ieee.std_logic_1164.all;
entity uartbyjackob_tb is
end entity;
architecture foo of uartbyjackob_tb is
signal clk: std_logic := '0';
signal reset: std_logic := '0';
signal txd: std_logic;
begin
DUT:
entity work.uartbyjackob
port map (
clk => clk, -- clk_txd driven by clk
a => 'X',
b => 'X',
c => 'X', -- a, b, c aren't used
reset => reset,
txd => txd,
txdosc => open
);
CLOCK:
process
begin
wait for 52.35 us;
clk <= not clk;
if now > 20000 us then
wait;
end if;
end process;
STIMULUS:
process
begin
wait for 104.7 us;
reset <= '1';
wait for 104.7 us;
reset <= '0';
wait;
end process;
end architecture;
The model has been modified for faster simulation, ignoring the baud rate clock generator.
There's an added flip flop (davl) for enabling the UART to run. There's an added baud (bit) counter bdcnt.
I changed the order of the start, stop and data values loaded into QTxD so the start bit came out first, followed by 8 data bits and the stop bit.
You can read off TxD from left to right start bit, data(q)(0) ... data(q(7), stop bit. The enable or ldqtxd will occur at the same time as a stop bit.
There's only one observable draw back to this implementation, if you reset while a value in the shift register hasn't finished loading you'll cause a framing error for the receiver. Don't reset it for 10 baud times after davl goes false.
The simulation is shown with a 9600 baud clk_txd, the characters go out back to back.
It has fewer flip flops than the original (disregarding k). There is no data register separate from QTxD ( - 8 FFs) plus bdcnt (+ 4) plus davl (+ 1). There are two comparisons (optimized to two) bdcnt = 9, q =, /= 9. Those could be expressed separately so it doesn't require optimization during synthesis.
I changed the look up table style, a matter of personal preference also the excuse for changing counters to type unsigned and using only package numeric_std for arithmetic.
The little testbench likewise doesn't expect the k counter to generate the baud clock.
Running the testbench gives:
Where there's an added signal datalut to show the value being shifted out after ldqtxd.
After your change making the q counter (7 downto 0)
We still see from your waveform that it doesn't work.
This is due to the enable and the shift register.
If you use a single counter with the upper four bits indexing the output character your character is transmitted in 10 out of the 16 clk_txd times indexed by the lower four bits of the counter. The remaining clock times TxD should be '1' (idle line marks in RS-232 parlance).
The order for data to be transmitted will be a space (the start bit), data(0) through data(7) and a mark (the stop bit). (Shown left to right on TxD).
For simulation the k counter is not used. I included it commented out below.
I made several changes for proper simulation. These include synchronously loading the shift register containing QTxD, synchronously clearing the rightmost bit of QTxD to provide a full width and moving enable to occur once every sixteen clocks (clk_txd). The enable is preceded by a new clear for the start bit and both been offset to prevent it from occurring during reset which has the effect of causing a framing error on the first character for any receiver.
Simulation is done with the same testbench I provide above.
The changes to your new code are shown by comments:
architecture behavioral of uartbyjackob is
-- signal k: std_logic_vector(14 downto 0);
signal q: unsigned (7 downto 0); -- std_logic_vector(7 downto 0);
signal clk_txd: std_logic;
signal enable: std_logic;
signal qtxd: std_logic_vector(7 downto 0);
-- using an 8 bit shift register requires a method of outputting a
-- synchronous start bit (the width is important for receive framing)
-- and synchronous stop bit
signal data: std_logic_vector(7 downto 0);
signal qprim: std_logic_vector(3 downto 0);
signal clear: std_logic; -- synchronous clear for start bit
begin
-- let's keep this here for when you put it the FPGA
-- -- freq of clock -- NOTE k never in known binary state for simulation
-- process (clk, reset)
-- begin
-- if rising_edge(clk then
-- if a = '1' and k < 10416 then
-- k <= k + 1;
-- clk_txd <= k(13);
-- elsif b = '1' and k < 5208 then
-- k <= k + 1;
-- clk_txd <= k(12);
-- elsif c = '1' and k < 20832 then
-- k <= k + 1;
-- clk_txd <= k(14);
-- else
-- k <= (others => '0');
-- end if;
-- end if;
-- end process;
process (clk) -- , reset)
begin
clk_txd <= clk; -- if simply a concurrent assignment statement this
end process; -- would look similar to the elaborated equivalent
-- process. The difference, no sensitivity list and
-- an explict wait on clk statement at the end.
-- This process wants to be removed and replaced by
-- the above commented out process for synthesis
process (clk_txd, reset) -- , reset, enable) -- enable a reset?
begin
-- if enable = '0' then
if reset = '1' then -- puts q counter in known state for simulation
q <= "00000000";
elsif rising_edge(clk_txd) then
if q /= 255 then -- stop after sending once
q <= q + 1;
end if;
end if;
end process;
-- enable <= '1' when q <= 255 else '0'; -- this appears incorrect
enable <= '1' when q(3 downto 0) = "0010" else
'0';
clear <= '1' when q(3 downto 0) = "0001" else
'0';
-- USING ONE COUNTER requires some clocks output MARKS
-- (idle bits) each 16 clocks. It requires the load (enable)
-- occur once every 16 clocks.
-- q(3 downto 0) is selected for enable to prevent outputting spaces
-- TxD during reset (q is reset to all '0's). This would cause a receive
-- framing error.
process (q(7 downto 4))
begin
case q(7 downto 4) is
when "0000" => data <= x"40";
when "0001" => data <= x"41";
when "0010" => data <= x"42";
when "0011" => data <= x"43";
when "0100" => data <= x"44";
when "0101" => data <= x"45";
when "0110" => data <= x"46";
when "0111" => data <= x"47";
when "1000" => data <= x"48";
when "1001" => data <= x"49";
when "1010" => data <= x"50";
when "1011" => data <= x"51";
when "1100" => data <= x"52";
when "1101" => data <= x"53";
when "1110" => data <= x"54";
when "1111" => data <= x"55";
when others => data <= x"56";
end case;
end process;
process (clk_txd) -- , enable, data) -- synchronous enable and clear
begin
-- if enable = '1' then -- this appears incorrect
-- qtxd <= data;
if reset = '1' then
qtxd <= (others => '1'); -- outputs mark after reset
elsif rising_edge(clk_txd) then
if clear = '1' then -- synchronous clear for start bit
qtxd(0) <= '0';
elsif enable = '1' then -- synchronous load
qtxd <= data;
else
qtxd <= '1' & qtxd(7 downto 1); -- shift right
end if;
end if;
end process;
-- the synchronous load prevents the first start bit from being stretched
-- q(3 downto 0) the following in hex notation
-- q(3 downto 0) = 2 is the start bit
-- = 3 is data(0)
-- ...
-- = A is data(7)
-- = B is the stop bit
-- = C - 1 are mark (idle) bits (q(3 downto 0) rolls over)
-- = 1 enable occurs loading qtxd
--
-- The offset is caused by synchronous load (1 clk_txd) and the load point
-- (q(3 downto 0) = 1 in enable term).
--
-- The load point wants to occur in the first 6 counts of q(3 downto 0) to
-- insure a trailing mark when q is stopped.
--
-- q(3 downto 0) = 1 is selected for enable to prevent spurious spaces
-- during reset from causing a receive framing error.
txd <= qtxd(0);
txdosc <= qtxd(0);
end architecture behavioral;
The comment table:
-- the synchronous load prevents the first start bit from being stretched
-- q(3 downto 0) the following in hex notation
-- q(3 downto 0) = 2 is the start bit
-- = 3 is data(0)
-- ...
-- = A is data(7)
-- = B is the stop bit
-- = C - 1 are mark (idle) bits (q(3 downto 0) rolls over)
-- = 1 enable occurs loading qtxd
--
-- The offset is caused by synchronous load (1 clk_txd) and the load point
-- (q(3 downto 0) = 1 in enable term).
--
-- The load point wants to occur in the first 6 counts of q(3 downto 0) to
-- insure a trailing mark when q is stopped.
--
-- q(3 downto 0) = 1 is selected for enable to prevent spurious spaces
-- during reset from causing a receive framing error.
tells you where to find bits of the data(q(7 downto 0)) selected character. In the following waveform q is shown as hex to match:
You'll find with the fixes the first character transmitted is 0x40, the second 0x41,...
I little bit confused with dual port RAM,my target is write and read data.I want to write data.like on the certain address will be 128 and on the rest adresses will be just 0.Is it works correctly,because Im not sure that those case statements are useful? How to write correctly data in this RAM?
I reading this article
and I think I need true dual port Ram.I have next code.
library ieee;
use ieee.std_logic_1164.all;
entity true_dual_port_ram_single_clock is
generic (
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
port (
clk : in std_logic;
addr_a : in natural range 0 to 2**ADDR_WIDTH - 1;
addr_b : in natural range 0 to 2**ADDR_WIDTH - 1;
data_a : in std_logic_vector((DATA_WIDTH-1) downto 0);
data_b : in std_logic_vector((DATA_WIDTH-1) downto 0);
we_a : in std_logic := '1';
we_b : in std_logic := '1';
q_a : out std_logic_vector((DATA_WIDTH -1) downto 0);
q_b : out std_logic_vector((DATA_WIDTH -1) downto 0)
);
end true_dual_port_ram_single_clock;
architecture rtl of true_dual_port_ram_single_clock is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
type memory_t is array((2**ADDR_WIDTH - 1) downto 0) of word_t;
-- Declare the RAM signal.
shared variable ram : memory_t;
begin
process(clk)
begin
if(rising_edge(clk)) then -- Port A
if(we_a = '1') then
ram(addr_a) := data_a;
-- Read-during-write on the same port returns NEW data
case addr_a is
when 0 =>
q_a <= "10000000";
when 16 =>
q_a <= "10000000";
when others =>
q_a <="00000000";
end case;
q_a <= data_a;
else
-- Read-during-write on the mixed port returns OLD data
case addr_a is
when 0 =>
q_a <= "10000000";
when 16 =>
q_a <= "10000000";
when others =>
q_a <="00000000";
end case;
q_a <= ram(addr_a);
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then -- Port B
if(we_b = '1') then
case addr_a is
when 0 =>
q_b <= "10000000";
when 16 =>
q_b <= "10000000";
when others =>
q_b <="00000000";
end case;
ram(addr_b) := data_b;
-- Read-during-write on the same port returns NEW data
q_b <= data_b;
else
-- Read-during-write on the mixed port returns OLD data
if(we_b = '1') then
case addr_b is
when 0 =>
q_b <= "10000000";
when 16 =>
q_b <= "10000000";
when others =>
q_b <="00000000";
end case;
q_b <= ram(addr_b);
end if;
end if;
end if;
end process;
end rtl;
I'm sending data to and A/D converter and I need the command data to be delayed at least 50ns from clk_19khz. Here is what I have so far.
How do I insert a delay of 50ns which is a requirement for the A/D between the clk_19khz and my first Dout bit to the A/D?
I'm using a Xilinx FPGA. Thanks for the help!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PSOL is
Port ( clk : in STD_LOGIC;
clk_19khz : OUT std_logic;
Dout :out std_logic);
end PSOL;
architecture Behavioral of PSOL is
signal temp : std_logic;
signal count : integer range 0 to 1301 := 0; --1301
signal temp2 : std_logic;
signal dcount : integer range 0 to 11 := 0; --
signal start : std_logic := '1'; -- indicates the start of
signal parity : std_logic := '1'; --used to varify data sent
signal stop : std_logic := '0'; --indicate when word/command has
--signal chip_select : bit :='1'; -- active low
begin
process (clk)
begin
if (clk' EVENT AND clk='1') then
if (count = 1301) then --1301
temp <= not(temp);
count <=0;
else
count <= count + 1;
end if;
end if;
end process;
clk_19khz <= temp;
temp2 <= temp;
process (temp2)
begin
If (temp2' EVENT and temp2 ='0') then
dcount <= dcount + 1;
parity <= '1';
stop <= '0';
start <='1';
if (dcount < 12 and start = '1' and stop = '0') then
CASE dcount is
when 1 => Dout <= start; -- need delay 50ns before this
when 2 => Dout <= '0';
when 3 => Dout <= '1';
when 4 => Dout <= '0';
when 5 => Dout <= '1';
when 6 => Dout <= '0';
when 7 => Dout <= '0';
when 8 => Dout <= '1';
when 9 => Dout <= '1';
when 10 => Dout <= parity;
when 11 => Dout <= '0';
when others => null;
end case;
end if;
end if;
--dcount <= 0;
--start <='1';
end process;
end Behavioral;
Your clock (50 MHz) has a period of 20 ns. So you'll need a modulo-3 counter to count a delay of at least 3 clock pulses which gives a delay of 60 ns.
Declarations:
signal delay_en : std_logic;
signal delay_us : unsigned(1 downto 0) := (others => '0');
signal delay_ov : std_logic;
Usage:
process(clk)
begin
if rising_edge(clk) then
if (delay_en = '1') then
delay_us <= delay_us + 1;
else
delay_us <= (others => '0');
end if;
end if;
end process;
delay_ov <= '1' when (delay_us = 2) else '0';
Your current implementation needs to drive delay_en while it's waiting for the timespan. If the delay is over, it emits the signal delay_ov (ov = overflow). This can be used by your solution to go on the in algorithm. Your code should also deassert delay_en, what clears the counter to 0.
I've this code:
library IEEE;
use IEEE.std_logic_1164.all;
entity Controller is
port (
CLK : in std_logic;
OutENABLE : out std_logic_vector (2 downto 0);
ModuleRESET : in std_logic;
ModuleENABLE : in std_logic
);
end Controller;
architecture Controller_archi of Controller is
signal Counter : integer range 0 to 4200 := 0;
begin
process (CLK, ModuleRESET)
begin
if ModuleRESET = '0' then
OutENABLE <= (others => '0');
Counter <= 0;
elsif rising_edge(CLK) then
if ModuleENABLE = '1' then
Counter <= Counter + 1;
case Counter is
when 0 =>
OutENABLE <= "001";
when 450 =>
OutENABLE <= "010";
when 900 =>
OutENABLE <= "100";
when 1350 =>
OutENABLE <= "001";
Counter <= 0;
when others =>
end case;
else
OutENABLE <= "000";
end if;
end if;
end process;
end Controller_archi;
But it's not working like I need.
What I need:
When ModuleENABLE goes '1' instantly OutENABLE goes "001" and not at first rising_edge(CLK) (Now, in this code, if ModuleENABLE goes '1' OutENABLE doesn't change from "000" to "001", it change to "001" after first rising_edge(CLK))
Counter go up when rising_edge(CLK) and OutENABLE it's updated every CLK event. (Now, in this code, counter go up when rising_edge(CLK) but OutENABLE it's updated when rising_edge(CLK) and not when CLK goes up and goes down)
So I've modified code to do that:
library IEEE;
use IEEE.std_logic_1164.all;
entity Controller is
port (
CLK : in std_logic;
OutENABLE : out std_logic_vector (2 downto 0);
ModuleRESET : in std_logic;
ModuleENABLE : in std_logic
);
end Controller;
architecture Controller_archi of Controller is
signal Counter : integer range 0 to 4200 := 0;
begin
process (CLK, ModuleENABLE, ModuleRESET)
begin
if ModuleRESET = '0' then
OutENABLE <= (others => '0');
Counter <= 0;
elsif ModuleENABLE = '1' then
if rising_edge(CLK) then
Counter <= Counter + 1;
end if;
case Counter is
when 0 =>
OutENABLE <= "001";
when 450 =>
OutENABLE <= "010";
when 900 =>
OutENABLE <= "100";
when 1350 =>
OutENABLE <= "001";
Counter <= 0;
when others =>
end case;
else
Counter <= 0;
OutENABLE <= "000";
end if;
end process;
end Controller_archi;
Now code work like I need in ModelSim, but when I synthesize it or compile it and simulate again it doesn't work.
My question is:
What it's wrong with second code and how I can fix it?
If I can't fix second code how I can modify first code to work like I need?
What it's wrong with second code and how I can fix it?
Your synthesis tool is fussy about how the clock and reset lines are connected. You have to use a structure like:
if ModuleRESET = '0' then
...
elsif rising_edge(CLK) then
or the synthesis tool cannot recognise the clock and reset lines.
If I can't fix second code how I can modify first code to work like I need?
You need to move "OutENABLE" outside of the first process, and into a process of its own. From what you've said, OutENABLE should not be a register - it should be a combinatorial function of Counter, ModuleRESET and ModuleENABLE. Try this.
process (CLK, ModuleRESET)
begin
if ModuleRESET = '0' then
Counter <= 0;
elsif rising_edge(CLK) then
if ModuleENABLE = '1' then
Counter <= Counter + 1;
case Counter is
when 1350 =>
Counter <= 0;
when others =>
null;
end case;
end if;
end if;
end process;
process (Counter, ModuleRESET, ModuleEnable)
begin
OutENABLE <= "000";
if ModuleRESET = '1' and ModuleENABLE = '1' then
case Counter is
when 0 .. 449 =>
OutENABLE <= "001";
when 450 .. 899 =>
OutENABLE <= "010";
when 900 .. 1349 =>
OutENABLE <= "100";
when others =>
OutENABLE <= "001";
end case;
end if;
end process;