Trying to display on 640x480 vga display with fpga - vhdl

Question

I am literally writing this in desperation. i've tried some many times to make it work and it just doesn't.
im using Altera DE2 board - Cyclone II EP2C35F672C6 & been trying to display simple image on 640x480 vga screen.
im using a vga controller design i made for a different board- Altera DE1 which worked really good.
the difference on this DE2 board is a different DAC component which has 10bit rgb data instead of 4bit like in the DE1 board, and it has extra needed ouputs - VGA_SYNC, VGA_BLANK, VGA_CLK.
So i made the needed changes & found an example where it says to set VGA_BLANK to '1' constant and VGA_SYNC to '0'. VGA_CLK is connected to the 25.175 Mhz pixel clk which is the pll clk output.
i've tried so many variations & tried to use another example where they set vga_blank to '1' when in visable aread & '0' when not and it still didnt work. i just get a black screen saying no video input when i run the design.
below is the implementation of my timing generator, data_generator & vga_top_level
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.vga_consts.all;
entity vga_toplevel is
port
(
-- in --
clk, rst : in std_logic;
-- out --
vga_clk, vga_blank, vga_sync : out std_logic;
r_data, g_data, b_data : out std_logic_vector(9 downto 0);
h_sync, v_sync : out std_logic
);
end entity;
architecture structural of vga_toplevel is
component pll
port
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
component timing_generator
port
(
clk, rst : in std_logic;
h_cnt : out integer range 0 to h_frame-1;
v_cnt : out integer range 0 to v_frame-1;
vga_blank, vga_sync : out std_logic;
h_sync, v_sync : out std_logic
);
end component;
component data_generator
generic
(
vis_x : integer := visable_x;
vis_y : integer := visable_y
);
port
(
clk, rst : in std_logic;
h_cnt : in integer range 0 to h_frame-1;
v_cnt : in integer range 0 to v_frame-1;
-- RGB values
r_data, g_data, b_data : out std_logic_vector(9 downto 0)
);
end component;
signal h_cnt, v_cnt : integer range 0 to h_frame-1;
signal pll_clk, rst_out, locked : std_logic;
-------------------------------------------------------------------
begin
rst_out <= not locked; -- uncomment for PLL use
vga_clk <= pll_clk;
-- rst_out <= rst; -- comment for PLL use
-- pll_clk <= clk; -- comment for PLL use
PLL1: pll
port map
(
inclk0 => clk,
areset => rst,
c0 => pll_clk,
locked => locked
);
T_GEN: timing_generator
port map
(
-- in --
clk => pll_clk,
rst => rst_out,
-- out --
vga_blank => vga_blank,
vga_sync => vga_sync,
v_cnt => v_cnt,
h_cnt => h_cnt,
v_sync => v_sync,
h_sync => h_sync
);
D_GEN: data_generator
port map
(
-- in --
clk => pll_clk,
rst => rst_out,
v_cnt => v_cnt,
h_cnt => h_cnt,
r_data => r_data,
g_data => g_data,
b_data => b_data
);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.vga_consts.all;
entity timing_generator is
port
(
clk, rst : in std_logic;
h_cnt : out integer range 0 to h_frame-1;
v_cnt : out integer range 0 to v_frame-1;
vga_blank : out std_logic;
vga_sync : out std_logic;
h_sync, v_sync : out std_logic
);
end entity;
architecture behave of timing_generator is
signal h_cnt_inner : integer range 0 to h_frame-1;
signal v_cnt_inner : integer range 0 to v_frame-1;
begin
vga_blank <= '1';
vga_sync <= '0';
h_cnt <= h_cnt_inner;
v_cnt <= v_cnt_inner;
-- counter for pixels --
process (clk, rst)
begin
if rst = '1' then
h_cnt_inner <= 0;
elsif rising_edge(clk) then
if h_cnt_inner = h_frame-1 then
h_cnt_inner <= 0;
else
h_cnt_inner <= h_cnt_inner + 1;
end if;
end if;
end process;
-- counter for lines --
process (clk, rst)
begin
if rst = '1' then
v_cnt_inner <= 0;
elsif rising_edge(clk) then
if v_cnt_inner = v_frame-1 then
v_cnt_inner <= 0;
elsif h_cnt_inner = 654 then
v_cnt_inner <= v_cnt_inner + 1;
end if;
end if;
end process;
-- h_sync generator --
process (clk, rst)
begin
if rst = '1' then
h_sync <= '1';
elsif rising_edge(clk) then
if h_cnt_inner = h_sync_d(0)-1 then
h_sync <= '0';
elsif h_cnt_inner = h_sync_d(1) then
h_sync <= '1';
end if;
end if;
end process;
-- v_sync generator --
process(clk, rst)
begin
if rst = '1' then
v_sync <= '1';
elsif rising_edge(clk) then
if v_cnt_inner = v_sync_d(0) then
v_sync <= '0';
elsif v_cnt_inner = v_sync_d(1) + 1 then
v_sync <= '1';
end if;
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.vga_consts.all;
entity data_generator is
generic (
vis_x : integer := visable_x;
vis_y : integer := visable_y
);
port
(
clk, rst : in std_logic;
h_cnt : in integer range 0 to h_frame-1;
v_cnt : in integer range 0 to v_frame-1;
-- RGB values for each pixel
r_data, g_data, b_data : out std_logic_vector(9 downto 0)
);
end entity;
architecture behave of data_generator is
begin
-- process to handle only 1 color - blue screen
process(clk, rst)
begin
if rst = '1' then
r_data <= (others => '0');
g_data <= (others => '0');
b_data <= (others => '0');
elsif rising_edge(clk) then
if (h_cnt >= h_vis_d(0)) and (h_cnt < h_vis_d(1)) and (v_cnt >= v_vis_d(0)) and (v_cnt < v_vis_d(1)) then
-- if in visiable area
r_data <= (others => '1');
g_data <= (others => '1');
b_data <= (others => '1');
else
r_data <= (others => '0');
g_data <= (others => '0');
b_data <= (others => '0');
end if;
end if;
end process;
end architecture;