dual port RAM write data - vhdl

Question

I little bit confused with dual port RAM,my target is write and read data.I want to write data.like on the certain address will be 128 and on the rest adresses will be just 0.Is it works correctly,because Im not sure that those case statements are useful? How to write correctly data in this RAM?
I reading this article
and I think I need true dual port Ram.I have next code.
library ieee;
use ieee.std_logic_1164.all;
entity true_dual_port_ram_single_clock is
generic (
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
port (
clk : in std_logic;
addr_a : in natural range 0 to 2**ADDR_WIDTH - 1;
addr_b : in natural range 0 to 2**ADDR_WIDTH - 1;
data_a : in std_logic_vector((DATA_WIDTH-1) downto 0);
data_b : in std_logic_vector((DATA_WIDTH-1) downto 0);
we_a : in std_logic := '1';
we_b : in std_logic := '1';
q_a : out std_logic_vector((DATA_WIDTH -1) downto 0);
q_b : out std_logic_vector((DATA_WIDTH -1) downto 0)
);
end true_dual_port_ram_single_clock;
architecture rtl of true_dual_port_ram_single_clock is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
type memory_t is array((2**ADDR_WIDTH - 1) downto 0) of word_t;
-- Declare the RAM signal.
shared variable ram : memory_t;
begin
process(clk)
begin
if(rising_edge(clk)) then -- Port A
if(we_a = '1') then
ram(addr_a) := data_a;
-- Read-during-write on the same port returns NEW data
case addr_a is
when 0 =>
q_a <= "10000000";
when 16 =>
q_a <= "10000000";
when others =>
q_a <="00000000";
end case;
q_a <= data_a;
else
-- Read-during-write on the mixed port returns OLD data
case addr_a is
when 0 =>
q_a <= "10000000";
when 16 =>
q_a <= "10000000";
when others =>
q_a <="00000000";
end case;
q_a <= ram(addr_a);
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then -- Port B
if(we_b = '1') then
case addr_a is
when 0 =>
q_b <= "10000000";
when 16 =>
q_b <= "10000000";
when others =>
q_b <="00000000";
end case;
ram(addr_b) := data_b;
-- Read-during-write on the same port returns NEW data
q_b <= data_b;
else
-- Read-during-write on the mixed port returns OLD data
if(we_b = '1') then
case addr_b is
when 0 =>
q_b <= "10000000";
when 16 =>
q_b <= "10000000";
when others =>
q_b <="00000000";
end case;
q_b <= ram(addr_b);
end if;
end if;
end if;
end process;
end rtl;