This question is from an exame my school made a year ago.
I have a N-way set associative cache with 48 bit adresses and the tag 33 bits.
The cache can store 16384 double-type elements, if the adress is multiple of 64.
The question is: How many sets and lines per set exist?
Since the capacity is 16384 double-type and a double has 8 byte, I put the capacity in 16384 * 8 = 131072 byte
I think the 48 bit (6 byte) adress is the dimension of a line.
I saw on a website that the Cache capacity / number of bits in a line = lines number so I put 131072 / 6 = 21845 (approximate).
I can't get further than this, since I don't find the way to get the sets and if I'm right with the number of lines per set, as this is my problem.
Thanks
Related
Encountered this problem and the solution said
"32 bit address bits, 64 byte line means we have 6 bits for the word address in the line that aren't in the tag, 32,768 bytes in the cache at 64 byte lines is 512 total lines, which means we have 12 bits of address for the cache index, write back means we need a dirty bit, and we always need a valid bit. So each line has 64*8=512 data bits, 32-6- 12=14 tag bits, and 2 flag bits: data/total bits = 512/(512+14+2)=512/528."
When I tried to solve the problem I got 32kB/64byte=512 lines in total, i.e. 2^9=512. In addition, a 64 byte cache line size, 1 word=4 bytes, is 64/4=16 words per line i.e. 2^4.
To my understanding the total amount of bits in a cache is given by total amount of entries/lines in the caches*(tag address + data)-> 2^9*((32-9-4+2)+16*32). Thus, the amount of data bits per cache line is 512 (16 words *32 bits per word), and the tag is 32-9-4+2=21 (the 9 is the cache index for direct mapped cache, the 4 is to address each word and the 2 is the valid bit and dirty bit)
Effectively, the answer should be 512/533 and not 512/528.
Correct?
512 lines = 9 bits not 12 as they claim, so you are right on this point.
However, they are right that 64 byte lines gives 6 bits for the block offset — though it is a byte offset, not word as they say.
So, 32-6-9=17 tag bits, then plus the 2 for dirty & valid.
FYI, there's nothing in the above problem that indicates a conversion from bytes to words. While it is true that there will be 16 x 32-bit words per line (i.e. 64 bytes per line) it is irrelevant: we should presume that the 32-bit address is a byte address unless otherwise stated. (It would be unusual to state cache size in bytes for a word (not byte) addressable machine; it would also be unusual for a 32-bit machine to be word addressable — some teaching architectures like LC-3 are word addressable, however, they are 16-bits; other word addressable machines have odd sizes like 12 or 18 or 36 bit words — though those pre-date caches!)
Given a Cache with the following characteristics:
Main Memory: 16 bit Address
Cache Size: 256 Bytes
Cache Block Size: 8 Bytes
Cache Tag Size: 11 bits
What is the associativity of this Cache? Is it n-way Associative? If so what is n? Can someone please explain this so I can understand it?
Have a look at this nice illustration.
Here is how it works: Your address size is 16 bits, so you have 16 bits for the tag plus the index plus the offset within a cache block. If we assume that we want to address single bytes in the cache (which is usually the case), we need 3 bits to address 1 byte within a block (since each cache block is 8 = 2^3 bytes). That leaves 16 - 3 - 11 = 2 bytes for the index. With two bytes, we can address 2^2 = 4 different sets. We have 256 / 8 = 32 blocks in the cache (size of the cache / size of one block). Those 32 blocks are split into 4 sets, so each set holds 8 cache blocks. Your cache is thus 8-way associative.
Just to make sure, does every single address contain one byte? So say you had theoretical addresses FFF0 and FFFF: there are 16 values between these two addresses, which means between them they contain 16 bytes, or 8 x 16 bits? Every individual address is linked to a single byte?
Just to make sure, does every single address contain one byte?
...which means between them they contain 16 bytes, or 8 x 16 bits?
Every individual address is linked to a single byte?
Yes to all three questions.
Which is why the limitation with 32-bit addressing, you can only access 2^32 bytes == 4,294,967,296 bytes == 4 GiB. Each addressable memory location gives access to 1 byte.
If we could access 2 bytes with one address, then that limit would have been 8 GiB. And the architecture of modern chips and all software would have to be modified to determine whether they want both bytes or just the first or the second. So you'd need, say, 1 more bit to determine that. Guess what, if you had 33-bit machines, that's what we'd get...max address-able space of 8 GiB. Which is still effectively 1-byte-containing addresses. Workarounds do exist but that's not related to your questions.
* GiB = Binary GigaBytes.
Note that this is not related to "types" where a char is 1 byte and an int is 4 bytes. Programming languages compensate for that when trying to access the value of a stored variable/data stored at a location(s). And they are actually calculated as total bits rather than total bytes. So an int is considered as 32 bits rather than 4 bytes. When C fetches an int's value from memory, it will fetch all 4 bytes even though the address of the int refers to just one, the address of the first byte.
Yes. Addresses map to bytes 1 to 1, even if they expect you to work with a word size of two or four bytes at a time.
This is an example from the book Computer Organization and Architecture by Stallings
The cache can hold 64 Kbytes
Data are transfered between main memory and the cache in blocks of 4 bytes each. This means that the cache is organized as 16K = 2^14 lines of 4 bytes each *.
The main memory has 16M. That is 2^24 words. So 4M blocks of 4 bytes.
My confusion is in the second point. It is said that each block is of 4 bytes that is 4 words of 8 bits so one block is 32 bits = 2^5. Now I want to get the number of blocks in the cache. For that I divide the size of the cache with the size of one block, that is 2^16(64K)/2^5(4bytes) = 2^11 lines of 4 bytes each but the answer is 2^14. What am I doing wrong? Thanks!
Its 64K Bytes so it will be 2^16 Bytes.
You will have to make it to bits so it will be (2^16 * 2^3 bits) / 2^5 bits = 2^14
I wanted your guys opinion on if I'm doing this the right way.
"how much memory is needed for a 128kb (data) cache with 8 byte blocks and 64 bit address line."
Firstly I would put the data cache in power of 2 so that would be 2^17
Then the same with the 8 byte block which would be 2^3
So number of blocks would be 2^17 / 2^3 = 2^14.
Byte offset is always 2 bits.
Index is 14 bits as we got that earlier.
Would the tag be 32-14-2? =>16bits
so cache size is 2^14(64+16+1) = 1296KB?
(1 was gained because of valid bit field)