Given a Cache with the following characteristics:
Main Memory: 16 bit Address
Cache Size: 256 Bytes
Cache Block Size: 8 Bytes
Cache Tag Size: 11 bits
What is the associativity of this Cache? Is it n-way Associative? If so what is n? Can someone please explain this so I can understand it?
Have a look at this nice illustration.
Here is how it works: Your address size is 16 bits, so you have 16 bits for the tag plus the index plus the offset within a cache block. If we assume that we want to address single bytes in the cache (which is usually the case), we need 3 bits to address 1 byte within a block (since each cache block is 8 = 2^3 bytes). That leaves 16 - 3 - 11 = 2 bytes for the index. With two bytes, we can address 2^2 = 4 different sets. We have 256 / 8 = 32 blocks in the cache (size of the cache / size of one block). Those 32 blocks are split into 4 sets, so each set holds 8 cache blocks. Your cache is thus 8-way associative.
Related
Question:
Consider a computer system that has a cache with 4096 block. Each block can store 16 bytes. What will be the value stored in the TAG field of the cache block that holds the memory block containing the address 0xABCDEF.
a. if it is Direct Mapped Cache
b. if it is 16 way set associate cache
c. if it is fully associative cache
Here is my work/logic below:
We know that each block can store 16 bytes. So that 2^4. Meaning our block offset is 4
ABCDE is 24 bits, b/c 4 bits per piece
4096 blocks is 2^12
a. is it is directly mapped then 24 - 20 - 4 --> 0
b. if its 16 way then our calculation are 24-16(index) - 4(offset) --> 4
c. if it fully associate then we do have an index and its just 24 - 4 --> 20
I am not sure if I am approaching the question the right way. Any help would be much appreciated!
I am using this illustration as my reference for how cache is represented:
http://csillustrated.berkeley.edu/PDFs/handouts/cache-3-associativity-handout.pdf
Ok, so I figured it out.
a. Since our cache is directly mapped. We have 2^12 block blocks. That means the index will be 12, and with an offset of 4. The TAG value will be 8
b. Now since is 16 way associative. 2^4 = 16. So we do 2^12/ 2^4 ==> 2^8
This means the 8 will be in our index slot and the TAG value will be 12
c. If it is fully associative, that mean we won't have to account for the index slow. So its just 24 - 20 ==> 4
Hope this helps anyone who bumps into this
I'm sorry if I made an error in posting this. Please let me know if I need to change anything.
I've received my computer architecture homework back and I missed this question. My professor's explanation didn't make sense to me, and I disagree with what he told me, so I am here asking what you guys think.
Here is the question:
A computer uses 16-bit memory addresses. Main memory is 512KB, and the cache is 1KB with 32B per block. Given each of the following mapping functions, calculate the number of bits in each field of the memory address.
Here is how I worked through the direct mapping part of the problem:
Cache memory: 1KB (2^10), 16-bit memory addresses (1 word = 2B) -> 1024B/2B = 512 words, 16 words per block (32B) -> 512/16 = 32 cache memory blocks.
Main memory: 512 KB (2^19), 16-bit memory addresses (1 word = 2B) -> 524288B/2B = 256K words, 16 words per block (32B) -> 256K/16 = 16384 or 16K main memory blocks.
I understand the word tag as such: 32B per block allows for 16 16-bit memory addresses per block. This (I believe) supports that: 1 word = 16 bits = 2 B -> 32B/2B = 16 words in each block. This equates to 2^4 = 4 bits for determining which word in the block, leaving 12 bits for tag and block bits in the memory address.
Now, in order to map 16K main memory blocks directly into 32 cache memory blocks, there will have to be 512 main memory blocks mapped to each cache memory block. So 512/16K blocks per 1/32 blocks.
Here is where I am confused. Doesn't this require 9 tag bits, as 2^9 = 512 (main memory blocks possibly mapped into one cache memory block)?
For the block bits, which point to a particular block in the cache, this requires 5 bits. 2^5 = 32, blocks in cache memory.
This would require 18 bits in the memory address.
Here is my professor's answer for this question:
2^5 = 32 -> 5 Word bits
(1KB)/(32B) = 32 blocks -> 5 Block bits
16 – 5 – 5 = 6 Tag bits
I did not realize I could simply subtract the required block and word bits to get the tag bits. But it still doesn't make sense to me. 2^6 = 64 blocks per cache block. 64*32 gives 2048. I can't wrap my head around this. Can someone please help?
Okay, the terminology that i learnt is slightly different but the principal should be the same for this explanation.
So cache will have multiple sets (sort of like a cell). And each set will have 1 cache line (containing 1 block of data) or multiple cache lines (each contain 1 block of data) (direct mapping or n-associativity mapping).
In mapping the main memory blocks to the cache, the main memory address (16 bit) is divided into 3 fields: tag, index bits and offset bits. A memory cell is 1 byte and a block is made up of a few cells
Offset bits are used to access the individual bytes of a memory block. Think of it as the offset on top of the block base address to get the byte you want (i assume your memory should be byte-addressable rather than word-addressable as it doesn't make sense to access 2B word as this would be inflexible) And here your prof/textbook call it as word bit. Hence if a block has 32 Bytes, there would be log2(block size) = 5 bits needed to access the individuals cells in the mapped block.
Index bits (in direct mapped cache is called block bits too as the number of set is the same as the number of blocks in the cache) is used to identify which set/cache line/ cache block that the main memory block is mapped to the cache. There are 1KB/32B = 32 cache blocks in the cache. As direct mapping is used, each set contain only 1 cache block and therefore there will be 32 set in this cache. Thus to access the correct set in cache, 5 bits is needed and therefore index bits = 5 bits
Tag is a name to determine if the data block in cache is the correct one we are looking one from the main memory. As the address of main memory is 16 bit and we already know index and offset fields, it is easy to deduce that tag will need 16 - 5 - 5 6 bits. How we determine the tag is not really a concern as the block size and cache size (and hence no. of sets in cache is given here).
So Im having trouble understanding some parts to direct mapped caching. I have a byte addressed memory system that has 64KB memory with a 2KB direct-mapped cache. Cache blocks are 32 bytes.
From what I understand and please correct me if i'm wrong, I have 2048B/32B = 64 cache blocks. I need to figure out how many total bits are needed for each cache entry (tag, "dirty" bit, etc).
I believe i'll need 6 index bits (2^6 = 64 (# of blocks))
and 5 offset bits (2^5 = 32 (size of cache block))
Im just having trouble figuring out the rest that are needed.
The bits of a physical address can be split into 3 groups - the least significant group of bits that determine "offset of byte within cache block" and doesn't need to be stored in the tag, the middle group of bits that determine "index of cache block within the cache" and doesn't need to be stored in the tag, and the most significant group of bits that is used to check if the data in the cache is the data you want which must be stored in the tag.
With 64 KiB of physical address space a physical address would have 16 bits; and if your cache is 2048 bytes then (for "direct mapped") the least significant group of bits and the middle group of bits combined must add up to a total of 11 bits. That means the most significant group of bits (which must be stored in the tag) needs to be 5 bits (because 16 bits - 11 bits = 5 bits).
For other bits; you always need something to indicate if the entry is used or empty; if the cache is "write-back" you need a dirty bit but if the cache is "write-through" you don't; if there are multiple CPUs and cache coherency you need more bits for that (e.g. exclusive/shared); and if there's any kind of error detection or correction you need more bits for that (e.g. a "parity bit"). This means the total tag size is at least 6 bits (but may be more).
This is an example from the book Computer Organization and Architecture by Stallings
The cache can hold 64 Kbytes
Data are transfered between main memory and the cache in blocks of 4 bytes each. This means that the cache is organized as 16K = 2^14 lines of 4 bytes each *.
The main memory has 16M. That is 2^24 words. So 4M blocks of 4 bytes.
My confusion is in the second point. It is said that each block is of 4 bytes that is 4 words of 8 bits so one block is 32 bits = 2^5. Now I want to get the number of blocks in the cache. For that I divide the size of the cache with the size of one block, that is 2^16(64K)/2^5(4bytes) = 2^11 lines of 4 bytes each but the answer is 2^14. What am I doing wrong? Thanks!
Its 64K Bytes so it will be 2^16 Bytes.
You will have to make it to bits so it will be (2^16 * 2^3 bits) / 2^5 bits = 2^14
I wanted your guys opinion on if I'm doing this the right way.
"how much memory is needed for a 128kb (data) cache with 8 byte blocks and 64 bit address line."
Firstly I would put the data cache in power of 2 so that would be 2^17
Then the same with the 8 byte block which would be 2^3
So number of blocks would be 2^17 / 2^3 = 2^14.
Byte offset is always 2 bits.
Index is 14 bits as we got that earlier.
Would the tag be 32-14-2? =>16bits
so cache size is 2^14(64+16+1) = 1296KB?
(1 was gained because of valid bit field)