How to make a counter reset when he reaches a certain value? - vhdl

Question

I have this code which counts clock cycles between two asychronous (and random ) trigger events. I wish to make the counter stop if it reaches the value 1200d and reset to zero.
The code is provided without my attempts to reset the counter.
I've tried to add an ( if counter reaches 1200 then counter to be done zero ) statement in the clock process but no result.
I simulate with two cases. First: I have a pair of trigger events with 85 clock cycles between them and the second pair of trigger events with 1500 clock cycles between them . In the second case I want the counter to stop when it reaches 1200 and go back to 0.
I apologise but I can't yet post an image of my simulation
Thanks in advance for any help.
The module
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity main is
Port ( clk : in STD_LOGIC;
trigger : in STD_LOGIC;
output : out STD_LOGIC_VECTOR(11 DOWNTO 0) );
end main;
architecture Behavioral of main is
signal counter : STD_LOGIC_VECTOR(11 DOWNTO 0) := "000000000000";
signal enable : STD_LOGIC:='0';
begin
trigger_proc : process(trigger)
variable state : std_logic := '0';
begin
if(falling_edge(trigger))then
if(state = '0')then
enable <= '1';
state := '1';
elsif(state = '1')then
enable <= '0';
state := '0';
end if;
end if;
end process;
counter_proc : process(clk)
begin
if(rising_edge(clk))then
if(enable = '1')then
counter <= counter + "1";
elsif(enable = '0' )then
counter <= "000000000000";
end if;
end if;
end process;
output <= counter;
end Behavioral;
and the TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test IS
END test;
ARCHITECTURE behavior OF test IS
COMPONENT main
PORT(
clk : IN std_logic;
trigger : IN std_logic;
output : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
signal clk : std_logic := '0';
signal trigger : std_logic := '1';
signal output : std_logic_vector(11 downto 0);
constant clk_period : time := 25 ns;
BEGIN
kyklwma: main PORT MAP (
clk => clk,
trigger => trigger,
output => output
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
trigger_stim: process
begin
wait for 100 ns;
trigger <= '0';-- first trigger event with counter <1200
wait for clk_period;
trigger <= '1';
wait for clk_period*85;
trigger <= '0';--second trigger event with counter <1200
wait for clk_period;
trigger <= '1';
wait for 10000 ns;
trigger <= '0';-- first trigger event with counter > 1200
wait for clk_period;
trigger <= '1';
wait for clk_period*1500;
trigger <= '0';--second trigger event with counter > 1200
wait for clk_period;
trigger <= '1';
wait;
end process;
END;