Error: "expression is not constant" with shift unit - vhdl

Question

I wrote the code below in order the do shift the binary number, I tried to compile it for the device cyclonII - EP2C20F484C7, but got this error:
Error (10779): VHDL error at shiftNbits.vhd(30): expression is not constant
Error (10658): VHDL Operator error at shiftNbits.vhd(30): failed to evaluate call to operator ""&""
vhd(30) is the line:
resultTemp <= A( N-1-numberOfShifts downto 0) & (numberOfShifts-1 downto 0 => '0');
I saw the some people asked about it, and they got the answer that the compiler don't like the idea of N-1-numberOfShifts or numberOfShifts-1 being negative. The thing is that I ensure that numberOfShifts
if numberOfShifts>=N then
resultTemp <= (N-1 downto 0 => '0');
And I even tried to add range to numberOfShifts definitions:
variable numberOfShifts: integer range 1 to N-1;
In order to ensure that numberOfShifts-1 is not negative.
By the way when I doning A(0 downto 0) I get actually one bit vector, How I define NULL vector if A( -1 downto 0) is not legal?
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity shiftNbits is
generic(N: integer := 8);
port (
typeOfShift : in std_logic_vector (1 downto 0);
enable : in std_logic;
A : in std_logic_vector(N-1 downto 0);
B : in std_logic_vector (N-1 downto 0);
result : out std_logic_vector(N-1 downto 0)
);
end shiftNbits;
architecture shiftNbitsGate of shiftNbits is
signal resultTemp: std_logic_vector(N-1 downto 0);
begin
process (typeOfShift, enable, A, B)
variable numberOfShifts: integer;
begin
numberOfShifts:= to_integer(unsigned(B));
if enable= '1' then
case typeOfShift is
when "00" => --RLA
if numberOfShifts>=N then
resultTemp <= (N-1 downto 0 => '0');
else
resultTemp <= A( N-1-numberOfShifts downto 0) & (numberOfShifts-1 downto 0 => '0');
end if;
when "01" => --RLC
numberOfShifts := numberOfShifts mod N;
resultTemp <= A( N-1-numberOfShifts downto 0) & A( N-1 downto N-numberOfShifts);
when "10" => --RRA
if numberOfShifts>=N then
resultTemp <= (N-1 downto 0 => A(N-1));
else
resultTemp <= (N-1 downto N-numberOfShifts => A(N-1)) & A( N-1 downto numberOfShifts);
end if;
when "11" => --RRC
numberOfShifts := numberOfShifts mod N;
resultTemp <= A( numberOfShifts-1 downto 0) & A( N-1 downto numberOfShifts);
when others => null;
end case;
else
resultTemp <= A; --what we should insert here?
end if;
end process;
result <= resultTemp;
end shiftNbitsGate;

Answer 1

resultTemp <= A( N-1-numberOfShifts downto 0) & (numberOfShifts-1 downto 0 => '0');
can't be implemented in one "line" (one set of gates / one logic equation) in hardware, as it may correspond to many different cases (one per number of shifts).
In VHDL, you're required to expand all these possibilities with if then else or a case select.
If the shift value had been constant, the code could indeed be synthesized, hence the error message!