ok, what I would like to do is assign a smaller std_vector to a large one, padding out the upper bits with zeros. But, I want something generic and simple that doesn't involve knowing the size of each first.
for instance if I have:
signal smaller_vec: std_logic_vector(15 downto 0);
signal larger_vec: std_logic_vector(31 downto 0);
I could do:
larger_vec <= X"0000" & smaller_vec;
But what if I don't know the size of the smaller vector. Is there a was of specifying that all upper bits are zero.
I know about the others clause, but that would get messy as I'd need a couple of lines:
larger_vec(smaller_vec'high downto 0) <= smaller_vec;
larger_vec(31 downto smaller_vec'length) <= (others => '0');
I thought I could use:
larger_vec <= "" & smaller_vec;
but this didn't work. any ideas?
Have you tried:
larger_vec <= (31 downto smaller_vec'length => '0') & smaller_vec;
In the past I have had synthesis tool issues with code like that, so I have used:
constant ZERO : std_logic_vector(larger_vec'range) := (others => '0');
. . .
larger_vec <= ZERO(31 downto smaller_vec'length) & smaller_vec;
James0's 2nd post was close, but the <= is facing the wrong direction, see below for a working example from duolos. I would edit, but at the time of this post I did not have enough reputation.
In https://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_ease/ in the Vectors in aggregates section it says:
variable V : std_logic_vector(7 downto 0);
begin
V := (others => '0'); -- "00000000"
V := ('1', '0', others => '0'); -- "10000000"
V := (4 => '1', others => '0'); -- "00010000"
V := (3 downto 0 => '0', others => '1'); -- "11110000"
-- V := ("0000", others => '1'); -- illegal!
larger_vec <= (smaller_vec'high downto 0 => smaller_vec, others => '0');
should work.
in my case I also like the following:
larger_vec <= (smaller_vec'high downto 0 <= smaller_vec, others => '0');
Which does my final answer in one line. This works, yes?
I have encountered similar issues and tried the following:
larger_vec <= (larger_vec'range => '0') + shorter_vec;
You need to use IEEE.std_logic_unsigned.all for this approach.
Zero-Pad or Truncate any std_logic_vector or std_logic to exactly 16 bits:
function pad16(x: std_logic_vector)
return std_logic_vector is
constant ZERO : std_logic_vector(15 downto 0) := (others => '0');
begin
if (x'length < 16) then
return ZERO(15 downto x'length) & x;
else
return x(15 downto 0);
end if;
end function;
--overload function for single bit
function pad16(x: std_logic)
return std_logic_vector is
constant ZERO : std_logic_vector(15 downto 0) := (others => '0');
begin
return ZERO(15 downto 1) & x;
end function;
-- USAGE:
--
-- reg16 <= pad16(X"3");
Related
I wrote the code below in order the do shift the binary number, I tried to compile it for the device cyclonII - EP2C20F484C7, but got this error:
Error (10779): VHDL error at shiftNbits.vhd(30): expression is not constant
Error (10658): VHDL Operator error at shiftNbits.vhd(30): failed to evaluate call to operator ""&""
vhd(30) is the line:
resultTemp <= A( N-1-numberOfShifts downto 0) & (numberOfShifts-1 downto 0 => '0');
I saw the some people asked about it, and they got the answer that the compiler don't like the idea of N-1-numberOfShifts or numberOfShifts-1 being negative. The thing is that I ensure that numberOfShifts
if numberOfShifts>=N then
resultTemp <= (N-1 downto 0 => '0');
And I even tried to add range to numberOfShifts definitions:
variable numberOfShifts: integer range 1 to N-1;
In order to ensure that numberOfShifts-1 is not negative.
By the way when I doning A(0 downto 0) I get actually one bit vector, How I define NULL vector if A( -1 downto 0) is not legal?
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity shiftNbits is
generic(N: integer := 8);
port (
typeOfShift : in std_logic_vector (1 downto 0);
enable : in std_logic;
A : in std_logic_vector(N-1 downto 0);
B : in std_logic_vector (N-1 downto 0);
result : out std_logic_vector(N-1 downto 0)
);
end shiftNbits;
architecture shiftNbitsGate of shiftNbits is
signal resultTemp: std_logic_vector(N-1 downto 0);
begin
process (typeOfShift, enable, A, B)
variable numberOfShifts: integer;
begin
numberOfShifts:= to_integer(unsigned(B));
if enable= '1' then
case typeOfShift is
when "00" => --RLA
if numberOfShifts>=N then
resultTemp <= (N-1 downto 0 => '0');
else
resultTemp <= A( N-1-numberOfShifts downto 0) & (numberOfShifts-1 downto 0 => '0');
end if;
when "01" => --RLC
numberOfShifts := numberOfShifts mod N;
resultTemp <= A( N-1-numberOfShifts downto 0) & A( N-1 downto N-numberOfShifts);
when "10" => --RRA
if numberOfShifts>=N then
resultTemp <= (N-1 downto 0 => A(N-1));
else
resultTemp <= (N-1 downto N-numberOfShifts => A(N-1)) & A( N-1 downto numberOfShifts);
end if;
when "11" => --RRC
numberOfShifts := numberOfShifts mod N;
resultTemp <= A( numberOfShifts-1 downto 0) & A( N-1 downto numberOfShifts);
when others => null;
end case;
else
resultTemp <= A; --what we should insert here?
end if;
end process;
result <= resultTemp;
end shiftNbitsGate;
resultTemp <= A( N-1-numberOfShifts downto 0) & (numberOfShifts-1 downto 0 => '0');
can't be implemented in one "line" (one set of gates / one logic equation) in hardware, as it may correspond to many different cases (one per number of shifts).
In VHDL, you're required to expand all these possibilities with if then else or a case select.
If the shift value had been constant, the code could indeed be synthesized, hence the error message!
I'm trying to implement an FSM with a RAM behavior. There are multiple addresses of this ram that should be initialized while describing this FSM. So, I'm using the array aggregation technique to initialize the first 20 addresses of the ram_block. However, I'm getting a bad syntax error on each line the aggregation has occurred or the partial section of the ram_block(i) has initialized. Any helps would be appreciated.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity RegisterController is
port(
r1_p: inout std_logic_vector(31 downto 0);
r2_p: inout std_logic_vector(31 downto 0);
write_p: in std_logic;
enable_p: in std_logic;
clk_p: in std_logic;
ram_rw: in std_logic; -- 0 => Read from ram | 1 => Write to the ram
reset_p: in std_logic
);
end RegisterController;
architecture RTL of RegisterController is
-- Create the ram word
subtype ram_word is std_logic_vector(66 downto 0);
-- Create the ram block of 32 ram_words
type ram_block is array (31 downto 0) of ram_word;
-- Address to read from the ram
signal R_ADDR_S: std_logic_vector(4 downto 0) := "00000";
begin
RAM_LOAD: process(clk)
begin
-- We're gonna load the 32 words of this ram with clock first
-- Outputs are being updated in the runtime :D
if(rising_edge(clk)) then
if(ram_rw = '1') then
-- STATE 0 DESCRIPTION
ram_block(0) <= ("000", std_logic_vector(to_unsigned(0, 32)), std_logic_vector(to_unsgined(0, 32)));
ram_block(1) <= ("000", std_logic_vector(to_unsigned(0, 32)), std_logic_vector(to_unsigned(0, 32)));
ram_block(2) <= ("001", std_logic_vector(to_unsigned(0, 32)), std_logic_vector(to_unsigned(0, 32)));
ram_block(3) <= ("001", std_logic_vector(to_unsigned(0, 32)), std_logic_vector(to_unsigned(0, 32)));
-- STATE 1 DESCRIPTION
ram_block(4) <= (66 downto 64) => "001";
ram_block(5) <= (66 downto 64) => "001";
ram_block(6) <= ("001", r2_p, r1_p);
ram_block(7) <= (66 downto 64) => "010";
-- STATE 2 DESCRIPTION
ram_block(8) <= (66 downto 64) => "010";
ram_block(9) <= (66 downto 64) => "010";
ram_block(10) <= (66 downto 64) => "011";
ram_block(11) <= (66 downto 64) => "011";
-- STATE 3 DESCRIPTION
ram_block(12) <= (66 downto 64) => "011";
ram_block(13) <= (66 downto 64) => "011";
ram_block(14) <= (66 downto 64) => "100";
ram_block(15) <= (66 downto 64) => "100";
-- STATE 4 DESCRIPTION
ram_block(16) <= (66 downto 64) => "100";
ram_block(17) <= (66 downto 64) => "100";
ram_block(18) <= (66 downto 64) => "001";
ram_block(19) <= (66 downto 64) => "001";
ram_block(31 downto 20) <= std_logic_vector(to_unsigned(0, 67));
end if;
end if;
end process;
START_FSM: process(clk)
-- TEMPORARY VARIABLE TO STORE THE READ VALUE FROM THE RAM BLOCK
variable temp_read_ram: std_logic_vector(66 downto 0);
variable temp_read_ram2: std_logic_vector(66 downto 0);
-- R3 Declaration as a variable
variable R3_V: std_logic_vector(31 downto 0);
begin
if(rising_edge(clk)) then
if(ram_rw = '0') then
-- START READING THE RAM FROM ADDRESS 0
temp_read_ram := ram_block(to_integer(unsigned(R_ADDR_S)));
R_ADDR_S(4 downto 2) <= temp_read_ram(66 downto 64);
R_ADDR_S(1 downto 0) <= (enable_p, write_p);
-- UPDATE THE OUTPUTS
if(R_ADDR_S = "00110") then
-- READ THE PREVIOUS VALUE IN THAT ADDRESS
temp_read_ram2 <= ram_block(R_ADDR_S);
-- UPDATE THE OUTPUT VALUES INSIDE RAM
ram_block(R_ADDR_S) <= (temp_read_ram2(66 downto 64), r2_p, r1_p);
-- NO NEED TO UPDATE r2_p and r1_p
elsif(R_ADDR_S = "00111") then
-- PUT THE CURRENT VALUE OF R1 TO THE R3
temp_read_ram2 <= ram_block(R_ADDR_S);
-- SAVE R1 TO THE R3_V
R3_V := temp_read_ram2(31 downto 0);
elsif(R_ADDR_S = "01110" or R_ADDR_S = "01111") then
-- READ THE PREVIOUS VALIE IN THOSE ADDRESSES
temp_read_ram2 <= ram_block(R_ADDR_S);
-- UPDATE THE OUTPUT VALUE OF R2 INSIDE RAM
ram_block(R_ADDR_S) <= (temp_read_ram2(66 downto 64), R3_V, temp_read_ram2(31 downto 0));
-- UPDATE THE OUTPUT VALUE OF r2_p
r2_p <= R3_V;
else
else
-- NO CHANGE
ram_block(R_ADDR_S) <= ram_block(R_ADDR_S);
end if;
end if;
end if;
end process;
end RTL;
There's not one, but many syntax errors in your code.
First off, ram_block is a type, not a signal. So why are you assigning values to it? You need to declare a signal first. I.e.
-- Create the ram block of 32 ram_words
type ram_block_type is array (31 downto 0) of ram_word;
signal ram_block : ram_block_type := (others => (others => '0'));
^ what I also include here, is initialization of the signal. Same can be done for:
signal R_ADDR_S: std_logic_vector(4 downto 0) := (others => '0');
In the process, you are assigning values to many locations in the RAM at the same time! That is not RAM-like. A random access memory usually only has 1 or 2 ports, accessing 1 resp. 2 elements at a time. You are designing generic distributed memory, so imho should not call it RAM.
Assigning to part of the array has a specific syntax. You can either assign the whole matrix in one go (this is VHDL-2008 by the way):
ram_block <= (4 => (66 downto 64 => "001", others => '0'), others => '0');
Note: you need to assign all values here, hence the others statement.
Second option, assign one sub-array
ram_block(4) <= (66 downto 64 => "001", others => '0');
Finally, and probably what you want, assign a specific sub-set of a sub-array:
ram_block(4)(66 downto 64) <= "001";
But in this case, you want to initialize the array, as else unassigned std_logic's will have the default value 'U'.
Then:
ram_block(31 downto 20) <= std_logic_vector(to_unsigned(0, 67));
This will not work. You're assigning an array structure to an array-of-arrays.
Variable R3_V is assigned in one situation, but not used directly: It is used a different clock cycle. In that case do not use a variable: that is bad coding style. It should be a signal.
And you must remember that signals assigned in a clocked process will not have access to their new value until the next delta cycle. Thus the assignment of signal R_ADDR_S(4 downto 2) <= temp_read_ram(66 downto 64); will not be available for the following if-statements!
Other things:
clk should probably be clk_p
to_unsgined -> to_unsigned
in line 79 you use the correct ram_block(to_integer(unsigned(R_ADDR_S))), but later (line 86) you do it wrong ram_block(R_ADDR_S)
in line 79 you also correctly assign a variable using :=, but later (line 86 again) you use the incorrect <=.
there's a double else at the end of the code.
I'm trying to calculate the average of a signal on 4 consecutive values. This signal is signed and I'm really not sure about the right calculation to do.
SIGNAL my_signed_signal : std_logic_vector(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL average_sum : signed(17 DOWNTO 0) := (OTHERS => '0');
SIGNAL average_result : signed(15 DOWNTO 0) := (OTHERS => '0');
...
-- within my process
average_sum <= average_sum + signed(my_signed_signal); -- loop 4 times
...
average_result <= average_sum(17 DOWNTO 2); -- how I finally get the result (div by 4)
I am aware that this should work for unsigned signals but I'm pretty sure it doesn't for signed ones because of the signed bit. Yet I don't really know what to change. Does anyone have an idea?
Yes, it works for signed types, too.
I have a std_logic_vector, x: std_logice_vector(A+B-1 downto 0), and I want to set the top A bits to '1' and the bottom B bits to '0', is there an easy way to do this?
I would like to do something like this:
x <= (A+B-1 downto B <= (others => '1'),
B-1 downto 0 <= (others => '0'));
My other plans are to define the sub signals and join them:
signal top: std_logic_vector(A-1 downto 0);
signal bottom: std_logic_vector(B-1 downto 0);
...
top <= (others => '0');
bottom <= (others => '1');
x <= top & bottom;
Or I could write a function that loops over all the bits but that seems like a lot of work for something this easy.
If there isn't an easy way and since I need to do this multiple times I might define a constant and use that.
Another option is to use aliases. For example:
architecture test of foo is
signal x: std_logic_vector(A+B-1 downto 0);
alias x_upper is x(A+B-1 downto B);
alias x_lower is x(B-1 downto 0);
begin
x_upper <= (others => '1');
x_lower <= (others => '0');
end architecture test;
You can treat the aliases just like signals. (And they are fully synthesizable).
I am writing a code for a 4 bit ALU and I have a problem when I want to write for shift left operation. I have two inputs (operandA and operandB ). I want to convert the operandB into decimal (for example "0010" into '2') and then shift operandA 2 times to the left. my code is compiled but I am not sure that it is true. Thank you in advance.
entity ALU is
port(
reset_n : in std_logic;
clk : in std_logic;
OperandA : in std_logic_vector(3 downto 0);
OperandB : in std_logic_vector(3 downto 0);
Operation : in std_logic_vector(2 downto 0);
Start : in std_logic;
Result_Low : out std_logic_vector(3 downto 0);
Result_High : out std_logic_vector(3 downto 0);
Ready : out std_logic;
Errorsig : out std_logic);
end ALU;
architecture behavior of ALU is
signal loop_nr : integer range 0 to 15;
begin
process (reset_n, clk, operation)
variable tempHigh : std_logic_vector(4 downto 0);
begin
if (reset_n = '0') then
Result_Low <= (others => '0');
Result_High <= (others => '0');
Errorsig <= '0';
elsif (clk'event and clk = '1') then
case operation is
when "001" =>
for i in 0 to loop_nr loop
loop_nr <= to_integer(unsigned(OperandB));
Result_Low <= OperandA(2 downto 0)&'0';
Result_High <= tempHigh(2 downto 0) & OperandA(3);
end loop;
Ready <= '1';
Errorsig <= '0';
when "010" =>
Result_Low <= OperandB(0)& OperandA(3 downto 1);
Result_High <= OperandB(3 downto 1);
Ready <= '1';
when others =>
Result_Low <= (others => '0');
ready <= '0';
Errorsig <= '0';
end case;
end if;
end process;
end behavior;
For shifting left twice the syntax should be the following:
A <= A sll 2; -- left shift logical 2 bits
I don't quite understand why is it required to convert operand B in decimal. It can be used as a binary or decimal value or for that matter hexadecimal value at any point of time irrelevant of the base it was saved in.
The operator sll may not always work as expected before VHDL-2008 (read more
here),
so consider instead using functions from ieee.numeric_std for shifting, like:
y <= std_logic_vector(shift_left(unsigned(OperandA), to_integer(unsigned(OperandB))));
Note also that Result_High is declared in port as std_logic_vector(3 downto
0), but is assigned in line 41 as Result_High <= OperandB(3 downto 1), with
assign having one bit less than size.
Assumption for code is that ieee.numeric_std is used.
The reason you've been urged to use the likes of sll is because in general
synthesis tools don't support loop statements with non-static bounds
(loop_nr). Loops are unfolded which requires a static value to determine how
many loop iterations are unfolded (how much hardware to generate).
As Morten points out your code doesn't analyze, contrary to you assertion
that it compiles.
After inserting the following four lines at the beginning of your code we see
an error at line 41:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--(blank, a spacer that doesn't show up in the code highlighter)
ghdl -a ALU.vhdl
ALU.vhdl:41:26: length of value does not match length of target
ghdl: compilation error
Which looks like
Result_High <= '0' & OperandB(3 downto 1);
was intended in the case statement, choice "010" (an srl equivalent hard
coded to a distance of 1, presumably to match the correct behavior of the sll
equivalent). After which your design description analyzes.
Further there are other algorithm description errors not reflected in VHDL
syntax or semantic errors.
Writing a simple test bench:
library ieee;
use ieee.std_logic_1164.all;
entity alu_tb is
end entity;
architecture foo of alu_tb is
signal reset_n: std_logic := '0';
signal clk: std_logic := '0';
signal OperandA: std_logic_vector(3 downto 0) :="1100"; -- X"C"
signal OperandB: std_logic_vector(3 downto 0) :="0010"; -- 2
signal Operation: std_logic_vector(2 downto 0):= "001"; -- shft right
signal Start: std_logic; -- Not currently used
signal Result_Low: std_logic_vector(3 downto 0);
signal Result_High: std_logic_vector(3 downto 0);
signal Ready: std_logic;
signal Errorsig: std_logic;
begin
DUT:
entity work.ALU
port map (
reset_n => reset_n,
clk => clk,
OperandA => OperandA,
OperandB => OperandB,
Operation => Operation,
Start => Start,
Result_Low => Result_Low,
Result_High => Result_High,
Ready => Ready,
Errorsig => Errorsig
);
CLOCK:
process
begin
wait for 10 ns;
clk <= not clk;
if Now > 100 ns then
wait;
end if;
end process;
STIMULUS:
process
begin
wait for 20 ns;
reset_n <= '1';
wait;
end process;
end architecture;
Gives us a demonstration:
The first thing that sticks out is that Result_High gets some 'U's. This is
caused by tempHigh not being initialized or assigned.
The next thing to notice is that the shift result is wrong (both Result_Low
and Result_High). I'd expect you'd want a "0011" in Result_High and "0000" in
Result_Low.
You see the result of exactly one left shift - ('U','U','U','1') in
Result_High and "1000" in Result_Low.
This is caused by executing a loop statement in delta cycles (no intervening
simulation time passage). In a process statement there is only one driver for
each signal. The net effect of that is that there is only one future value
for the current simulation time and the last value assigned is going to be
the one that is scheduled in the projected output waveform for the current
simulation time. (Essentially, the assignment in the loop statement to a
signal occurs once, and because successive values depend on assignment
occurring it looks like there was only one assignment).
There are two ways to fix this behavior. The first is to use variables
assigned inside the loop and assign the corresponding signals to the
variables following the loop statement. As noted before the loop bound isn't
static and you can't synthesis the loop.
The second way is to eliminate the loop by executing the shift assignments
sequentially. Essentially 1 shift per clock, signaling Ready after the last
shift occurs.
There's also away to side step the static bounds issue for loops by using a
case statement (or in VHDL 2008 using a sequential conditional signal
assignment of sequential selected signal assignment should your synthesis
tool vendor support them). This has the advantage of operating in one clock.
Note all of these require having an integer variable holding
to_integer(unsigned(OperandB)).
And all of this can be side stepped when your synthesis tool vendor supports
sll (and srl for the other case) or SHIFT_LEFT and SHIFT_RIGHT from package
numeric_std, and you are allowed to use them.
A universal (pre VHDL 2008) fix without using sll or SHIFT_LEFT might be:
begin
process (reset_n, clk, operation)
variable tempHigh : std_logic_vector(4 downto 0);
variable loop_int: integer range 0 to 15;
begin
if (reset_n = '0') then
Result_Low <= (others => '0');
Result_High <= (others => '0');
Errorsig <= '0';
elsif (clk'event and clk = '1') then
case operation is
when "001" =>
loop_int := to_integer(unsigned(OperandB));
case loop_int is
when 0 =>
Result_Low <= OperandA;
Result_High <= (others => '0');
when 1 =>
Result_Low <= OperandA(2 downto 0) & '0';
Result_High <= "000" & OperandA(3);
when 2 =>
Result_Low <= OperandA(1 downto 0) & "00";
Result_High <= "00" & OperandA(3 downto 2);
when 3 =>
Result_Low <= OperandA(0) & "000";
Result_High <= "0" & OperandA(3 downto 1);
when 4 =>
Result_Low <= (others => '0');
Result_High <= OperandA(3 downto 0);
when 5 =>
Result_Low <= (others => '0');
Result_High <= OperandA(2 downto 0) & '0';
when 6 =>
Result_Low <= (others => '0');
Result_High <= OperandA(1 downto 0) & "00";
when 7 =>
Result_Low <= (others => '0');
Result_High <= OperandA(0) & "000";
when others =>
Result_Low <= (others => '0');
Result_High <= (others => '0');
end case;
-- for i in 0 to loop_nr loop
-- loop_nr <= to_integer(unsigned(OperandB));
-- Result_Low <= OperandA(2 downto 0)&'0';
-- Result_High <= tempHigh(2 downto 0) & OperandA(3);
-- end loop;
Ready <= '1';
Errorsig <= '0';
Which gives:
The right answer (all without using signal loop_nr).
Note that all the choices in the case statement aren't covered by the simple
test bench.
And of course like most things there's more than two ways to get the desired
result.
You could use successive 2 to 1 multiplexers for both Result_High and
Result_Low, with each stage fed from the output of the previous stage (or
OperandA for the first stage) as the A input the select being the appropriate
'bit' from OperandB, and the B input to the multiplexers the previous stage
output shifted by 1 logically ('0' filled).
The multiplexers can be functions, components or procedure statements. By
using a three to one multiplexer you can implement both symmetrical shift
Operation specified operations (left and right). Should you want to include signed shifts,
instead of '0' filled right shifts you can fill with the sign bit value. ...
You should also be assigning Ready <= '0' for those cases where valid
successive Operation values can be dispatched.
And because your comment on one of the answers requires the use of a loop with an integer value:
process (reset_n, clk, operation)
variable tempHigh : std_logic_vector(4 downto 0);
variable tempLow: std_logic_vector(3 downto 0); --added
variable loop_int: integer range 0 to 15; --added
begin
if (reset_n = '0') then
Result_Low <= (others => '0');
Result_High <= (others => '0');
Errorsig <= '0';
elsif (clk'event and clk = '1') then
case operation is
when "001" =>
tempLow := OperandA; --added
tempHigh := (others => '0'); --added
loop_int := to_integer(unsigned(OperandB)); --added
-- for i in 0 to loop_nr loop
-- loop_nr <= to_integer(unsigned(OperandB));
-- Result_Low <= OperandA(2 downto 0)&'0';
-- Result_High <= tempHigh(2 downto 0) & OperandA(3);
-- end loop;
-- More added:
if loop_int /= 0 then
for i in 1 to loop_int loop
tempHigh (3 downto 0) := tempHigh (2 downto 0) & tempLow(3);
-- 'read' tempLow(3) before it's updated
tempLow := tempLow(2 downto 0) & '0';
end loop;
Result_Low <= tempLow;
Result_High <= tempHigh(3 downto 0);
else
Result_Low <= OperandA;
Result_High <= (others => '0');
end if;
Ready <= '1';
Errorsig <= '0';
Which gives:
And to demonstrate both halves of Result are working OperandA's default value has been changed to "0110":
Also notice the loop starts at 1 instead of 0 to prevent you from having an extra shift and there's a check for non-zero loop_int to prevent the for loop from executing at least once.
And is it possible to make a synthesizable loop in these circumstances?
Yes.
The loop has to address all possible shifts (the range of loop_int) and test whether or not i falls under the shift threshold:
process (reset_n, clk, operation)
variable tempHigh : std_logic_vector(4 downto 0);
variable tempLow: std_logic_vector(3 downto 0); --added
subtype loop_range is integer range 0 to 15;
variable loop_int: integer range 0 to 15; --added
begin
if (reset_n = '0') then
Result_Low <= (others => '0');
Result_High <= (others => '0');
Errorsig <= '0';
elsif (clk'event and clk = '1') then
case operation is
when "001" =>
tempLow := OperandA; --added
tempHigh := (others => '0'); --added
loop_int := to_integer(unsigned(OperandB)); --added
for i in loop_range loop
if i < loop_int then
tempHigh (3 downto 0) := tempHigh (2 downto 0) & tempLow(3);
-- 'read' tempLow(3) before it's updated
tempLow := tempLow(2 downto 0) & '0';
end if;
end loop;
Result_Low <= tempLow;
Result_High <= tempHigh(3 downto 0);