"Can't determine the definition of operator +" when designing a 16-bit ALU - vhdl

Question

I am designing a 16-bit ALU which does few operations. I have a syntax error:
"Can't determine the definition of operator "+"".
The following code does Signed & Unsigned addition and subtraction and shift operation. It does a few other operations like OR, XOR etc., which I am not showing, as they doesn't have any problem.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU16 is port
( A: in std_logic_vector (15 downto 0);
B: in std_logic_vector (15 downto 0);
AluOp: in std_logic_vector (4 downto 0);
shamt: in std_logic_vector (2 downto 0);
Zero: out std_logic;
Overflow: out std_logic;
R: out std_logic_vector (15 downto 0)
);
end ALU16;
architecture RTL of ALU16 is
signal temp : std_logic_vector( 16 downto 0);
signal usgnA, usgnB, Reg1 : unsigned(15 downto 0);
signal sgnA, sgnB, Reg2 : signed(15 downto 0);
begin
process(AluOp)
variable p : integer range 0 to 15;
begin
--usgnA <= unsigned(A);
--usgnB <= unsigned(B);
sgnA <= signed(A);
sgnB <= signed(B);
case AluOp is
when "00000" =>
--Reg1 <= usgnA + usgnB;
temp <= ('0' & A) + ('0' & B);
Overflow <= temp(16);
--temp <= A + B;
R<=temp(15 downto 0);
--Overflow <= A(15) and B(15);
-- when "00001" =>
-- --Reg1 <= usgnA - usgnB;
-- R<=A-B;
-- if (A < B) then Overflow<= '1';
-- else Overflow<= '0';
-- end if;
--
-- when "00010" =>
-- Reg2 <= sgnA + sgnB;
-- R<=std_logic(Reg2);
-- Overflow <= A(14) and B(14);
--
-- when "00011" =>
-- R <= sgnA - sgnB;
-- R<=std_logic(Reg2);
-- if (sgnA < sgnB) then Overflow<= '1';
-- else Overflow<= '0';
-- end if;
--
-- when "01011" =>
-- temp <= A;
-- temp <= shift_right(A,to_integer(shamt));
-- p :=to_integer(shamt);
-- for i in 1 to 3 loop
-- temp(i-1) <= '0';
-- end loop;
-- R<= temp;
--
when others =>
NULL;
-- if( R = "0000000000000000" ) then
-- Zero <= '1';
-- else Zero <='0';
-- end if;
end case;
end process;
end RTL;

Answer 1

As you are using numeric_std (which you should be), you will need to either change the type of temp to unsigned or cast the result of the addition to std_logic_vector. For signed addition, you can detect overflow by comparing the input signs with the output sign. If the input signs match and the output sign is different, you have overflow. Otherwise, you don't. I might also recommend using variables instead of signals for all intermediate results (so you don't run into any problems with sequential signal assignment):
process (AluOp)
variable Temp : std_logic_vector(15 downto 0);
begin
...
when "00010" =>
Temp := std_logic_vector(sgnA + sgnB);
R <= Temp;
Overflow <= (sgnA(15) xnor sgnB(15)) and (sgnA(15) xor Temp(15));

Answer 2

You are doing sum of to std_logic_vector.
and you have not used ieee.std_logic_arith.all, So it is showing the error.
but in one hdl file you can not use use IEEE.NUMERIC_STD.ALL and ieee.std_logic_arith.all.
It will make the compiler confused.
so better tryout temp <= std_logic_vector(unsigned(A) + unsigned(B));
It might solve your problem.
try out different combinations like this.