VHDL synthesis tool won't infer FSM - vhdl

Question

I'm trying to create a FSM in VHDL. However, the synthesis tool that I'm using (Vivado) won't infer it, and instead it thinks I've created a lot of registers and mux.
The goal of the hardware I'm designing is to implement a locker onto a FPGA. I've changed a lot of things in order not to create any latch, so if you see something wrong please tell me. Also, I'm Spanish so some names are in Spanish; if you don't understand something please tell me. I don't know if you need something else like the synthesis report. (Please don't tell me to create just one process, I have to design it using one sequential and one combinational process).
Here's the code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cerrojo is
port ( boton : in std_logic;
rst : in std_logic;
clk : in std_logic;
clave : in std_logic_vector(7 downto 0);
leds : out std_logic_vector(15 downto 0);
intentos: out std_logic_vector(6 downto 0));
end cerrojo;
architecture archCerrojo of cerrojo is
signal intentos_binario : unsigned(3 downto 0);
signal sin_rebote : std_logic;
signal guardado : unsigned(7 downto 0);
type estado is(inicial, tres, dos, uno, final);
signal estado_actual, estado_siguiente : estado;
component conv_7seg is
port (x : in std_logic_vector (3 downto 0);
display : out std_logic_vector (6 downto 0));
end component conv_7seg;
component debouncer is
port (
rst : in std_logic;
clk : in std_logic;
x : in std_logic;
xdeb : out std_logic;
xdebfallingedge : out std_logic;
xdebrisingedge : out std_logic);
end component debouncer;
begin
sieteSeg : conv_7seg
port map ( x => std_logic_vector(intentos_binario(3 downto 0)),
display => intentos);
rebotes : debouncer
port map (rst => rst, clk => clk, x => boton, xdeb => sin_rebote);
p_reg : process(clk, rst)
begin
if rst = '1' then
guardado <= "00000000";
estado_actual <= inicial;
elsif rising_edge(clk) and estado_actual = inicial then
guardado <= unsigned(clave);
estado_actual <= estado_siguiente;
elsif rising_edge(clk) then
guardado <= guardado;
estado_actual <= estado_siguiente;
end if;
end process p_reg;
p_comb : process(estado_actual, sin_rebote, clave, guardado)
begin
case estado_actual is
when inicial =>
intentos_binario <= "1000";
leds <= "1111111111111111";
--guardado <= unsigned(clave);
if (sin_rebote = '1') then
estado_siguiente <= tres;
else
estado_siguiente <= inicial;
end if;
when tres =>
intentos_binario <= "0011";
leds <= "0000000000000000";
-- guardado <= guardado;
if (sin_rebote = '1' and guardado = unsigned(clave)) then
estado_siguiente <= inicial;
elsif (sin_rebote = '1' and guardado /= unsigned(clave)) then
estado_siguiente <= dos;
else
estado_siguiente <= tres;
end if;
when dos =>
intentos_binario <= "0010";
leds <= "0000000000000000";
--guardado <= guardado;
if (sin_rebote = '1' and guardado = unsigned(clave)) then
estado_siguiente <= inicial;
elsif (sin_rebote = '1' and guardado /= unsigned(clave)) then
estado_siguiente <= uno;
else
estado_siguiente <= dos;
end if;
when uno =>
intentos_binario <= "0001";
leds <= "0000000000000000";
--guardado <= guardado;
if (sin_rebote = '1' and guardado = unsigned(clave)) then
estado_siguiente <= inicial;
elsif (sin_rebote = '1' and guardado /= unsigned(clave)) then
estado_siguiente <= final;
else
estado_siguiente <= uno;
end if;
when final =>
intentos_binario <= "0000";
leds <= "0000000000000000";
--guardado <= guardado;
estado_siguiente <= final;
end case;
end process p_comb;
end architecture archCerrojo;
Thank you in advance!