For my hobby project I try to make a quadcopter which balances itself with the MPU-6050. The flight controller shall be the FPGA Altera cyclone IV, because its fun. I'm coding it in VHDL.
Anyway I'm stuck on the I2C communication with the MPU-6050. As bases I used the I2C master VHDL code from: https://www.digikey.com/eewiki/pages/viewpage.action?pageId=10125324.
I try to read the gyro registers and print them out on 8 leds just to see if I have some communication coming in.
I have tried to run with a 1Hz prescaler all the I2C phases in the state machine and light up some leds just to see if all phases are run through. This is the case. I have assigned the pins 2.5V default, I use 10k pull up resistors. The MPU6050 works perferct on an arduino.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mpu6050_2 is
port( clk_50 : in std_logic;
areset : in std_logic;
i2c_SDA : INOUT STD_LOGIC;
i2c_SCL : INOUT STD_LOGIC;
leds : out std_LOGIC_VECTOR(7 downto 0)
);
end entity mpu6050_2;
architecture struc of mpu6050_2 is
component i2c_master is
GENERIC(
input_clk : INTEGER := 50_000_000;
bus_clk : INTEGER := 400_000);
PORT(
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
ena : IN STD_LOGIC;
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
rw : IN STD_LOGIC;
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
busy : OUT STD_LOGIC;
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ack_error : BUFFER STD_LOGIC;
sda : INOUT STD_LOGIC;
scl : INOUT STD_LOGIC);
end component ;
type machine is (config1, config2, gyroH, gyroL);
signal state : machine:= config1; --current state
signal SDA_int : std_LOGIC;
signal SCL_int : std_LOGIC;
signal i2c_ena : std_LOGIC;
signal i2c_busy : std_LOGIC;
signal busy_prev : std_LOGIC;
signal i2c_rw : std_LOGIC;
signal i2c_data_wr : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal gyro_data : std_LOGIC_VECTOR(15 downto 0);
signal i2c_data_rd : std_LOGIC_VECTOR (7 downto 0);
signal i2c_addr : STD_LOGIC_VECTOR(6 DOWNTO 0);
begin
process(areset, clk_50)
VARIABLE busy_cnt : INTEGER := 0; --keeps track of i2c busy signals during transaction
begin
if areset = '0' then
busy_cnt := 0;
i2c_ena <= '0';
state <= config1;
elsif rising_edge(clk_50) then
case state is
when config1 =>
busy_prev <= i2c_busy;
if (busy_prev = '0' and i2c_busy = '1') then
busy_cnt := busy_cnt + 1;
end if;
case busy_cnt is
when 0 =>
i2c_ena <= '1';
i2c_addr <= "1101000"; --MPU6050 adress
i2c_rw <= '0'; --write
i2c_data_wr <= x"6B"; -- hex6B powermanagement
when 1 =>
i2c_rw <= '0'; --write
i2c_data_wr <= "00000000"; -- ON with internal clock
when 2 =>
i2c_ena <= '0';
if(i2c_busy = '0') then
busy_cnt := 0;
state <= config2;
end if;
when others => NULL;
end case;
when config2 =>
busy_prev <= i2c_busy;
if (busy_prev = '0' and i2c_busy = '1') then
busy_cnt := busy_cnt + 1;
end if;
case busy_cnt is
when 0 =>
i2c_ena <= '1';
i2c_addr <= "1101000"; --MPU6050 adress
i2c_rw <= '0'; --write
i2c_data_wr <= x"1B"; -- Gyro config
when 1 =>
i2c_rw <= '0'; --write
i2c_data_wr <= "00000000"; -- 250 degree/sec, no self test
when 2 =>
i2c_ena <= '0';
if(i2c_busy = '0') then
busy_cnt := 0;
state <= gyroH;
end if;
when others => NULL;
end case;
when gyroH =>
busy_prev <= i2c_busy;
if (busy_prev = '0' and i2c_busy = '1') then
busy_cnt := busy_cnt + 1;
end if;
case busy_cnt is
when 0 =>
i2c_ena <= '1';
i2c_addr <= "1101000"; --MPU6050 adress
i2c_rw <= '0'; --write
i2c_data_wr <= x"43"; -- hex43 GYRO_OUT[15:8]
when 1 =>
i2c_rw <= '1'; --read
when 2 =>
i2c_ena <= '0';
if(i2c_busy = '0') then
gyro_data(15 downto 8) <= i2c_data_rd;
busy_cnt := 0;
state <= gyroL;
end if;
when others => NULL;
end case;
when gyroL =>
busy_prev <= i2c_busy;
if (busy_prev = '0' and i2c_busy = '1') then
busy_cnt := busy_cnt + 1;
end if;
case busy_cnt is
when 0 =>
i2c_ena <= '1';
i2c_addr <= "1101000"; --MPU6050 adress
i2c_rw <= '0'; --write
i2c_data_wr <= x"44"; -- hex44 GYRO_OUT[7:0]
when 1 =>
i2c_rw <= '1'; --read
when 2 =>
i2c_ena <= '0';
if(i2c_busy = '0') then
gyro_data(7 downto 0) <= i2c_data_rd;
busy_cnt := 0;
state <= gyroH;
end if;
when others => NULL;
end case;
end case;
end if;
end process;
u0: i2c_master
port map(clk => clk_50, reset_n => areset, ena => i2c_ena, addr => i2c_addr, rw => i2c_rw, data_wr => i2c_data_wr, busy => i2c_busy, data_rd => i2c_data_rd
, sda => SDA_int, scl => SCL_int);
leds(7) <= gyro_data(0); --D4
leds(6) <= gyro_data(1); -- D5
leds(5) <= gyro_data(4); -- D6
leds(4) <= gyro_data(7); -- D7
leds(3) <= gyro_data(8); -- D8
leds(2) <= gyro_data(11); -- D9
leds(1) <= gyro_data(13); -- D10
leds(0) <= gyro_data(15); -- D11
i2c_SDA <= SDA_int;
i2c_SCL <= SCL_int;
end struc;
Result:
all the leds dont change status despite if i rotate the MPU6050. So no communication. Can anyone help me what i'm doing wrong?
First: I'm using the same component in one of my designs and do confirm it works.
I think you are just using the wrong i2c address to begin with.
In datasheets, i2c addresses are usually given including the read/write bit (for the MPU-6050, this is 0x68/01101000 and 0x69/01101001). The i2c master component used, however, expects to build the final i2c address by itself by appending (&) the i2c rw bit to the given address (see line 124 in the original sources), thus you must pass the address from the datasheet shifted by one bit.
Try using 0x34/0110100 as i2c address for read and write instead.
I only looked very briefly into the rest of your code (so there might be other culprits as well), but this should be enough to get you going.
Related
I have to implement a mini-router in VHDL. The design requirements for this are:
I've written the implementation, and a testbench. However, looking at the simulation waveform, some of my initial signals are undefined and I'm not sure why.
This is the source code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity mini_router is
port (
clk : in std_logic;
reset : in std_logic; -- synchronous negative reset
data1 : in std_logic_vector(9 downto 0);
req1 : in std_logic;
grant1 : out std_logic;
data2 : in std_logic_vector(9 downto 0);
req2 : in std_logic;
grant2 : out std_logic;
data_out : out std_logic_vector(7 downto 0);
valid : out std_logic
);
end entity;
architecture arch of mini_router is
signal aux : std_logic_vector(9 downto 0);
signal aux1 : std_logic_vector(1 downto 0);
signal aux2 : std_logic_vector(1 downto 0);
signal aux_valid : std_logic;
signal aux_grant1 : std_logic;
signal aux_grant2 : std_logic;
begin
mini_router: process(clk)
variable r : std_logic:= '1';
begin
-- conta le volte in cui c'è stato data conflict
if rising_edge(clk) then -- chiuso
if reset = '0' then
aux <= (others => '0');
aux_valid <= '0';
aux_grant1 <= '0';
aux_grant2 <= '0';
elsif reset = '1' then
if (req1 xor req2) = '1' then --chiuso -- un solo req è alto
if req1 ='1' then --chiuso
aux <= data1;
aux_grant1 <= '1';
aux_grant2 <= '0';
aux_valid <= '1';
else
aux <= data2;
aux_grant1 <= '0';
aux_grant2 <= '1';
aux_valid <= '1';
end if;
----entrambi i req sono alti
elsif (req1 and req2) = '1' then -- chiuso
if ((unsigned(aux1)) > (unsigned(aux2))) then
aux <= data1;
aux_grant1 <= '1';
aux_grant2 <= '0';
aux_valid <= '1';
elsif ((unsigned(aux1)) < (unsigned(aux2))) then
aux <= data2;
aux_grant2 <= '1';
aux_grant1 <= '0';
aux_valid <= '1';
elsif ((unsigned(aux1)) = (unsigned(aux2))) then -- stesso livello di priorità -- alternativa:(aux1 xnor aux2)="11"
if r = '1' then
aux <= data1;
aux_grant1<= '1';
aux_grant2 <= '0';
aux_valid <= '1';
r := not (r);
else
aux <= data2;
aux_grant2 <= '1';
aux_grant1<= '0';
aux_valid <= '1';
r := not (r);
end if;
end if;
elsif (req1 nor req2) = '1' then
aux_valid <= '0';
aux <= (others => '0');
aux_grant1 <= '0';
aux_grant2 <= '0';
end if;
end if; -- if del reset
end if; -- if del clock
end process;
data_out <= aux(9 downto 2);
aux1 <= data1 (1 downto 0);
aux2 <= data2 (1 downto 0);
valid <= aux_valid;
grant1 <= aux_grant1;
grant2 <= aux_grant2;
end architecture;
This is the testbench:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mini_router_tb is
end mini_router_tb;
architecture arc of mini_router_tb is
constant T_CLK : time := 10 ns; --- frequenza di clock: 125 MHz
signal clk_tb : std_logic := '1';
signal reset_tb : std_logic := '0'; -- reset attivo basso sincrono
signal data1_tb : std_logic_vector(9 downto 0) := (others => '0');
signal req1_tb : std_logic:= '0';
signal grant1_tb : std_logic;
signal data2_tb : std_logic_vector(9 downto 0) := (others => '0');
signal req2_tb : std_logic:= '0';
signal grant2_tb : std_logic;
signal data_out_tb : std_logic_vector(7 downto 0);
signal valid_tb : std_logic;
signal end_sim : std_logic := '1'; -- signal to use to stop the simulation when there is nothing else to test
component mini_router is
port (
clk : in std_logic;
reset : in std_logic; -- synchronous negative reset
data1 : in std_logic_vector(9 downto 0);
req1 : in std_logic;
grant1 : out std_logic;
data2 : in std_logic_vector(9 downto 0);
req2 : in std_logic;
grant2 : out std_logic;
data_out : out std_logic_vector(7 downto 0);
valid : out std_logic
);
end component;
begin
clk_tb <= (not(clk_tb)and(end_sim)) after T_CLK/2;
DUT : mini_router
port map (
clk => clk_tb,
reset => reset_tb,
data1 => data1_tb,
req1 => req1_tb,
grant1 => grant1_tb,
data2 => data2_tb,
req2 => req2_tb,
grant2 => grant2_tb,
data_out => data_out_tb,
valid => valid_tb
);
-- process used to make the testbench signals change synchronously with the rising edge of the clock
stimuli_process: process(clk_tb,reset_tb)
variable t : integer := 0; -- variabile che conta i cicli di clock
begin
if (rising_edge(clk_tb)) then
case (t) is
when 1 => data1_tb <= (9 downto 3 => '0') & "100"; -- data1= 4; data_out=0 per il reset
data2_tb <= (9 downto 4 => '0') & "1101";-- data2= 13;
req1_tb <= '1' ; req2_tb<= '0';
when 2 => reset_tb <= '1';
data1_tb <= (9 downto 3 => '0') & "100"; -- data1= 4; data_out=1
data2_tb <= (9 downto 4 => '0') & "1101"; -- data2= 13;
req1_tb <= '1' ; req2_tb<= '0';
when 3 => data1_tb <= (9 downto 3 => '0') & "100"; -- data1= 4;
data2_tb <= (9 downto 4 => '0') & "1101";-- data2= 13; data_out=3
req1_tb <= '0' ; req2_tb<= '1';
when 4 => data1_tb <= (9 downto 5 => '0') & "11100"; --data1=28
data2_tb <= (9 downto 4 => '0') & "1101"; -- data2= 13; data_out=3 priorità maggiore
req1_tb <= '1' ; req2_tb<= '1';
when 5 => data1_tb <= (9 downto 5 => '0') & "00111"; --data1=7; data_out=1 priorità maggiore
data2_tb <= (9 downto 5 => '0') & "11101"; -- data2= 29;
req1_tb <= '1' ; req2_tb<= '1';
when 6 => data1_tb <= (9 downto 5 => '0') & "00111"; --data1=7; data_out=1
data2_tb <= (9 downto 5 => '0') & "11111"; -- data2= 31;
req1_tb <= '1' ; req2_tb<= '1';
when 7 => data1_tb <= (9 downto 5 => '0') & "00111"; --data_out=0;
data2_tb <= (9 downto 5 => '0') & "11111";
req1_tb <= '0' ; req2_tb<= '0';
when 8 => data1_tb <= (9 downto 5 => '0') & "10111"; --data1=7; data_out non assunto=5
data2_tb <= (9 downto 5 => '0') & "11111"; -- data2= 31; data_out=7
req1_tb <= '1' ; req2_tb<= '1';
when 9 => end_sim <= '0'; -- stops the simulation when t = 10
when others => null; -- non accade nulla negli altri casi
end case;
t := t + 1;
end if;
end process;
end architecture;
Your reset logic is synchronous, because the outmost condition is rising_edge(clk). Therefore the internal signals are undefined until the first raising edge of the clock.
Change to an asynchronous reset like this (excerpt):
if reset = '0' then
-- reset statements
elsif rising_edge(clk) then
-- work statements
end if;
Please be aware that even with an asynchronous reset the signals will be undefined until reset is activated or the clock raises. This reflects the actual behavior of a real device.
The reason your signals are initially set to U or X is because the values of all signals, variables, etc. are initialized to the left hand side of the type definition.
From the IEEE 1076 code (see here):
-------------------------------------------------------------------
-- logic state system (unresolved)
-------------------------------------------------------------------
type STD_ULOGIC is ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
--------------------------------
And std_logic is just a resolved version of std_ulogic. So any signal of type std_logic will have its default value be U, unless set otherwise.
Consider the following code:
signal A : std_logic;
signal B : std_logic := '1';
Signal A would be U until set otherwise. Signal B will be 0 until set otherwise.
This is why you are seeing U in your simulation. (As for X you see in your waveform window, many simulators that collapse vectors into a single value in the waveform view treat collections with U as X. Expand that vector and I suspect you will see several U's.)
I have a few problems with a fairly simple state machine I made. No matter what I do, the signal startS1, startS2, enS and mS always stays unsigned in simulation even when I hit the reset button and I can't figure out why. There's a component in the mix, but I did test the component and it works perfectly. I hope you can help me!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity machine_etat is
generic (N_bit : integer := 8);
Port ( LOAD : in STD_LOGIC_VECTOR (N_bit-1 downto 0);
RESET : in STD_LOGIC;
START : in STD_LOGIC;
CLK : in STD_LOGIC;
OUTPUT : out STD_LOGIC_VECTOR (N_bit-1 downto 0));
end machine_etat;
architecture Behavioral of machine_etat is
TYPE machine is (IddleT, DepartT, LoadT, ShiftT, EndT);
SIGNAL Etat1, Etat2 : machine:= IddleT;
SIGNAL mS: STD_LOGIC_VECTOR (1 downto 0);
SIGNAL enS : STD_LOGIC;
SIGNAL outputS : STD_LOGIC_VECTOR (N_bit-1 downto 0);
component Reg_decal is
generic (N_bit : integer := N_bit);
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
EN : in STD_LOGIC;
M : in STD_LOGIC_VECTOR (1 downto 0);
LOAD : in STD_LOGIC_VECTOR (N_bit-1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (N_bit-1 downto 0));
end component;
SIGNAL startS1, startS2 : STD_LOGIC;
begin
OUTPUT <= outputS;
Reg_dec: Reg_decal
generic map (N_bit => N_bit)
port map (CLK => CLK,
RESET => RESET,
EN => enS,
M => mS,
LOAD => LOAD,
OUTPUT => outputS);
Machine1: process (CLK)
begin
if RESET = '1' then
enS <= '0';
mS <= "00";
startS1 <= '0';
startS2 <= '0';
Etat1 <= IddleT;
elsif rising_edge(CLK) then
CASE Etat1 is
WHEN IddleT =>
if startS1 = '1' OR START = '1' then
Etat1 <= DepartT;
else
Etat1 <= IddleT;
end if;
WHEN DepartT =>
Etat1 <= LoadT;
startS1 <= '0';
WHEN LoadT =>
mS <= "11";
enS <= '1';
Etat1 <= ShiftT;
WHEN ShiftT =>
mS <= "00";
Etat1 <= EndT;
WHEN EndT =>
enS <= '0';
startS2 <= '1';
Etat1 <= IddleT;
WHEN Others =>
Etat1 <= IddleT;
end CASE;
end if;
end process;
Machine2: process (CLK)
begin
if RESET = '1' then
Etat2 <= IddleT;
elsif rising_edge(CLK) then
CASE Etat2 is
WHEN IddleT =>
if startS2 = '1' then
Etat2 <= DepartT;
else
Etat2 <= IddleT;
end if;
WHEN DepartT =>
startS2 <= '0';
Etat2 <= LoadT;
WHEN LoadT =>
enS <= '1';
Etat2 <= ShiftT;
WHEN ShiftT =>
mS <= "01";
Etat2 <= EndT;
WHEN EndT =>
Etat2 <= IddleT;
startS1 <= '1';
WHEN Others =>
end CASE;
end if;
end process;
end Behavioral;
Add RESET to your process sensitivity list.
i'm trying to make my own I2C communication and i have a problem with multiply drivers, it's not like i don't understand them i just don't see them (i'm still fresh at vhdl), so please just take a look at my code and tell mi why is there such mistake.
i try to operate on flags to have multiple signal drivers on bus but there's just something not right. The multiple drivers are on scl, sda, start_clk and stop_clk. Is it because those flags are for example in two different processes?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity I2C_com is
port (
reset_en: in std_logic;
clk: in std_logic;
sda: inout std_logic;
scl: out std_logic;
RD:in std_logic;
WR: in std_logic;
addr: buffer std_logic_vector(7 downto 0)
);
end I2C_com;
architecture MAIN of I2C_com is
signal data :std_logic_vector (12 downto 0):="0000000000010";
signal i2c_clk: std_logic ;
signal clk_count : unsigned(19 downto 0):="00000000000000000100";
type program_state is (start,init,error_rd_wr,slave,ack);
signal state: program_state;
signal write_data: std_logic_vector (7 downto 0):=(others => '0');
signal read_data: std_logic_vector (7 downto 0):=(others => '0');
signal clk_enable: std_logic;
signal reset: std_logic:='1';
signal start_clk: std_logic:= 'Z';
signal stop_clk: std_logic:= 'Z';
signal strech: std_logic := '0';
signal cnt_addr: integer := 0;
signal ack_error: std_logic;
signal sda_data: std_logic;
signal start_data: std_logic:= 'Z';
begin
i2c_clock: process(clk,reset_en,reset)
begin
if reset_en = '1' or reset = '1' then
elsif falling_edge(clk) then
if clk_count < unsigned(data) then
clk_count <= clk_count + 1;
clk_enable <= '1';
else
clk_count <= x"00000";
clk_enable <= '0';
end if;
i2c_clk <= clk_enable;
if start_clk = '1' then
sda <= '0';
scl <= '0';
start_clk <= '0';
end if;
if stop_clk = '1' then
sda <= '0';
scl <= '0';
stop_clk <= '0';
end if;
end if;
end process i2c_clock;
--
process(i2c_clk,reset_en,reset)
begin
if reset_en = '1' or reset = '1' then
reset <= '0';
cnt_addr <= 0;
state <= init;
elsif rising_edge(i2c_clk) then
case state is
when init =>
if RD = '1' or WR = '1' then
state <= start;
else
state <= error_rd_wr;
end if;
when start =>
start_clk <= '1';
state <= slave;
when slave =>
start_data <= '1';
if cnt_addr < 8 then
sda_data <= addr(cnt_addr);
cnt_addr <= cnt_addr + 1;
else
cnt_addr <= 0;
state <= ack;
end if;
when error_rd_wr =>
reset <= '1';
when ack =>
start_data <= '0';
ack_error <= sda;
if ack_error = '1' then
stop_clk <= '1';
reset <= '1';
else
end if;
if RD = '1' then
elsif WR = '1' then
else
stop_clk <= '1';
reset <= '1';
end if;
end case;
end if;
end process;
sda <= sda_data when start_data = '1' else 'Z';
scl <= i2c_clk when start_clk = '0' and stop_clk = '0' else 'Z';
end MAIN;
A signal for synthesis can be driven from only one process or one continuous assign; for simulation multiple drivers are possible using resolved signals like std_logic.
The scl and sda are driven both from the i2c_clock process and the continuous assign in the end of the file.
The start_clk and stop_clk are driven both from the i2c_clock process and the other unnamed process.
One possibility for scl and sda is to only drive these from the continuous assign, since synthesis tools often prefer tri-state output to be written like:
q <= value when en = '1' else 'Z';
I have some troubles with my nexys 3 vhdl driver for the Pmod TMP. I would like to communicate with via SPI 3 wire (Clock, Reset and DQ (MISO/MOSI)) so I've wrote some code lines and test it using the leds to display receive data. But That don't work and I don't know why... I've made a state machine that, if it's the first time, send the configuration data and then send the word "start" to start convert, then I pass in receive configuration and take the convert data (temperature in binary) and finally send the "stop" word. And that start again without the send configuration because it's not the first time.
My state machine don't work, there is not receive data and I don't know why.
I'll be glad if you could help me.
Best regards.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SPI is
port(
CLK : in std_logic;
RST : in std_logic;
SPI_SCK : out std_logic;
SPI_DQ: inout std_logic;
SPI_RST : out std_logic;
LED : out std_logic_vector(7 downto 0) :="00000000"
);
end entity SPI;
architecture behavioral of SPI is
type State is ( IDLE , sendConf, sendBit , receiveBit, clockHigh , resetHigh);
signal States : State := IDLE;
signal Counter : integer range 0 to 15 := 0;
signal data_reg : std_logic_vector(15 downto 0):="0000000000000000";
signal data : std_logic_vector(8 downto 0):="000000000";
signal data_trans : std_logic_vector(7 downto 0):="00000000";
signal first_time : std_logic := '1';
signal send : std_logic := '0';
signal receive : std_logic := '0';
signal right : std_logic := '0';
begin
process(CLK, RST)
variable conf : std_logic_vector(15 downto 0):= "0000110000000011";
variable start: std_logic_vector(7 downto 0):= "01010001";
variable stop : std_logic_vector(7 downto 0):= "00100010";
begin
if rising_edge(CLK) then
if RST = '1' then
States <= IDLE;
first_time <= '1';
else
case States is
when IDLE =>
SPI_RST <= '1';
SPI_SCK <= '0';
Counter <= 0;
if first_time = '1' then
data_reg <= conf;
send <= '1';
first_time <= '0';
States <= sendConf;
else
if send = '1' then
data_trans <= start;
send <= '0';
receive <= '1';
right <= '0';
States <= sendBit;
elsif receive = '1' then
receive <= '0';
right <= '1';
States <= receiveBit;
elsif send = '0' and receive = '0' then
data_trans <= stop;
send <= '1';
right <= '0';
States <= sendBit;
end if;
end if;
when sendConf =>
SPI_SCK <= '0';
SPI_DQ <= data_reg(15);
data_reg <= data_reg(14 downto 0) & "0";
States <= clockHigh;
when sendBit =>
SPI_SCK <= '0';
SPI_DQ <= data_trans(7);
data_trans <= data_trans(6 downto 0) & "0";
States <= clockHigh;
when receiveBit =>
SPI_SCK <= '0';
data <= data(7 downto 0) & SPI_DQ;
States <= clockHigh;
when clockHigh =>
SPI_SCK <= '1';
if first_time = '1' then
if Counter = 16 then
States <= resetHigh;
else
Counter <= Counter + 1;
States <= sendConf;
end if;
else
if right = '1' then
if Counter = 9 then
States <= resetHigh;
else
Counter <= Counter + 1;
States <= sendBit;
end if;
else
if Counter = 8 then
States <= resetHigh;
else
Counter <= Counter + 1;
States <= sendBit;
end if;
end if;
end if;
when resetHigh =>
SPI_RST <= '0';
States <= IDLE;
end case;
end if;
end if;
end process;
end architecture behavioral;`
The Maxim DS1626 does not communicate via SPI interface. So please look into data sheet pages 4, 5 and 10, 11. These timing diagrams are very different from SPI or I²C or whatever.
i'm in the process of configuring an RS232 to USB cable with VHDL and i seem to have a problem. I don't know how to configure a dual-port RAM. I have attempted searching on answers to that and i found some code but i don't completely understand how to apply this code. This code can be found in this link --> http://www.asic-world.com/examples/vhdl/ram_dp_ar_aw.html.
Please help as soon as possible, i'm in desperate need of this information.
----------------------------------------------------------------------------------
-- Create Date : 14:06:22 12/08/2013
-- Designer Name : Sarin anand k
-- Module Name : UART - Behavioral
-- Project Name : RS232 transmitter
----------------------------------------------------------------------------------
-- spartan 3 starter kit
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VComponents.all;
entity uart is
port(
sys_clk : in std_logic; --50Mhz
reset : in std_logic;
data_in : in std_logic_vector(7 downto 0); -- switch
load : in std_logic; --push button
Tx : out std_logic
);
end uart;
architecture Behavioral of uart is
type T_state is (IDLE,STORAGE,START, DATA, STOP);
-- baud rate = 115200, bit duration required is 1/115200 = 8680 ns
-- for a 50MHz clock, period is 20 ns. So each bit is 8680/20 = 434 clock cycles
constant bit_dur : std_logic_vector(15 downto 0) := X"01B3"; -- 434 clocks
constant start_bit : std_logic := '0';
constant stop_bit : std_logic := '1';
signal baud_cnt : std_logic_vector(23 downto 0) := X"000000"; -- 115200
signal baud_en : std_logic;
signal temp : std_logic_vector(7 downto 0);
signal baud_rate_cnt : std_logic_vector(7 downto 0):=(others => '0');
signal bit_cnt_start : std_logic;
signal baud_flag : std_logic;
signal state : T_state;
begin
-----------------------------------------------------------------------------------------------------
---- baud clock
------------------------------------------------------------------------------------------------------
baud_rate: process(sys_clk) begin
if rising_edge(sys_clk) then
if (reset = '1') then
baud_cnt <= X"000000";
baud_en <= '0';
end if;
if (baud_cnt = bit_dur)then
baud_en <= '1'; -- data in flag
baud_cnt <= X"000000";
elsif(bit_cnt_start = '1') then
baud_cnt<= baud_cnt + '1';
baud_en <= '0';
end if;
end if;
end process baud_rate;
---------------------------------------------------------------------------------------------------------------
-- baud clock counter
----------------------------------------------------------------------------------------------------------------
baud_counter: process(sys_clk) begin
if(rising_edge (sys_clk)) then
if(reset = '1') then
baud_rate_cnt <=( others => '0');
baud_flag <= '0';
end if;
if( baud_rate_cnt = "1000") then
baud_flag <= '1';
baud_rate_cnt <=( others => '0');
elsif( state = DATA and baud_en ='1') then
baud_rate_cnt <= baud_rate_cnt + '1';
baud_flag <= '0';
end if;
end if;
end process baud_counter;
--------------------------------------------------------------------------------------------------------------------
-- State machine to control the data flow
----------------------------------------------------------------------------------------------------------------------
control_flow: process (sys_clk) begin
if(rising_edge (sys_clk)) then
if (reset = '1') then
bit_cnt_start <= '0';
state <= IDLE;
end if;
case state is
when IDLE =>
state <= STORAGE;
when STORAGE =>
if (load = '1') then
state <= START;
bit_cnt_start <= '1';
end if;
when START =>
if (baud_en ='1') then
state <= DATA;
end if;
when DATA =>
if ((baud_en ='1') and (baud_flag = '1')) then
state <= STOP;
end if;
when STOP =>
if (baud_en = '1') then
state <= IDLE;
bit_cnt_start <= '0';
end if;
when others =>
state <= IDLE;
end case;
end if;
end process control_flow;
------------------------------------------------------------------------------------------------------------------------
-- Data Transmission
-------------------------------------------------------------------------------------------------------------------------
data_trans: process (sys_clk) begin
if (rising_edge(sys_clk)) then
if (reset = '1') then
temp <= (others => '0');
end if;
-- Data Mux
case state is
when IDLE =>
temp <= (others => '0');
when STORAGE =>
temp <= data_in;
when START =>
Tx <= start_bit;
when DATA =>
Tx <= temp(0);
if ( baud_en = '1') then
temp <= '0' & temp(7 downto 1) ;
Tx <= temp(0);
end if;
when STOP =>
Tx <= stop_bit;
when others =>
Tx <= '1';
end case;
end if;
end process data_trans;
end Behavioral;