In the file Makefile.am a am using somehting like this:
PATH := $(PWD)/.tools/bin:$(PATH)
When running configure.ac I get this error:
Makefile.am:3: warning: ':='-style assignments are not portable
I using the assignment operator = would cause a recursive problem.
So I wonder how to adapt PATH variable in Makefile.am without having this problem?
If I really needed to change the shell's PATH inside a rule, I would set a shell variable PATH there, not a make variable PATH:
foo.h: foo.src
PATH="$${PATH}:$$(pwd)/.tools/bin"; \
my-tool foo.src > foo.h
However, if I need my-tool from that directory, why not call my-tool with the proper path in the first place?
foo.h: foo.src .tools/bin/my-tool
./.tools/bin/my-tool foo.src > foo.h
Related
Apart from the standard directories used by make to locate files loaded by include directives, is there any way to specify additional include paths within the makefile itself? I'm aware of the -I command-line GNU make option but I would like to know if there's any make variable to specify the same.
I suggested using the .INCLUDE_DIRS variable, but as pointed out in the comment below, that variable is read-only.
The only other way I can think of is to have a top-level file invoke the real makefile, and have the top level one update MAKEFLAGS:
# Top level -- Call it GNUmakefile?
INCLUDE_DIRS := first second third
MAKEFLAGS += $(foreach dir,$(INCLUDE_DIRS),--include-dir=$(dir))
.DEFAULT all:;$(MAKE) -f Makefile $(MAKECMDGOALS)
Then the real Makefile is invoked with the three directories in .INCLUDE_DIRS.
In Gnumake, one can include a file as follows:
include some_file
I now wonder, is it possible to get the filepath of some_file from within that file, e.g. by doing $(shell pwd)? (I know that that command in particular doesn't work since it gets the path of the working directory, not the included file.)
You can use the MAKEFILE_LIST variable to obtain that. The last filename in that variable will be the current makefile, as long as you check it before you include any other files. Basically every time make reads a new makefile the name of that makefile is added to the end of the variable, but no value is ever removed from the variable even after the makefile is no longer being parsed:
THIS_MAKEFILE := $(word $(words $(MAKEFILE_LIST)),$(MAKEFILE_LIST))
I think you can use the readlink -f <file> command to get the path of the file. You just have to know from within the file what the filename is, which I'm assuming you can hardcode.
My include file references many other make files using something like:
include Enablers/MSRP/Android.mk
the problem is that the make file that references all other makefiles is deep in sub-folders, or, in other words the correct path would be something like:
include ../../../../../Enablers/MSRP/Android.mk
In order for me to build my makefile I have to add ../../../../.. to make search path:
ndk-build -I../../../../.. -j8 other params...
(ndk-build is a wrapper for gnu make on android buildsystem, it's equivalent to make build-local.mk other params)
So, what can i do to to avoid adding the ../../../../.. to make search path? I could go the makefile and update all makefile include statements, but I'm looking for the way to add that extra include path at the top of my makefile. Something like:
makeincludepaht += include Enablers/MSRP/Android.mk
include Enablers/MSRP/Android.mk
...
Append the new include path to the standard search path:
.INCLUDE_DIRS += ../../..
Look at the end of the Special Variables section for the .INCLUDE_DIRS special variable.
I'm not familiar with ndk-build, but I have similar setup. I just set a variable in make that contains this path and then use that variable in all my includes.
makefile:
INCLUDE_TOP=../../../../..
include $(INCLUDE_TOP)/someDir/includes.mk
You can also then use INCLUDE_TOP inside includes.mk for all your paths. It is usually better to make it default to some value by conditionally setting in there.
includes.mk:
# will only set if not already set
INCLUDE_TOP ?= ./
HEADERS=$(INCLUDE_TOP)/headers
I would like to tell (g)make to include some common initializations from a separate file knowing the relative location of the included file with respect to the main Makefile.
However in the manuals I cannot find any built-in variable that would, for example, give you the name of the current Makefile.
For example if I want to include the content of a file in the same directory as the current make file, instead of hard-wiring the location of the include:
# MAIN Makefile : ./scripts/make/TaskA.mk
include ./scripts/make/Common.inc
...
I would like to write something like the following assuming that _MAKEFILE_ contains the TaskA.mk location:
# MAIN Makefile : ./scripts/make/TaskA.mk
MAKEFILE_DIR=$(dirname $(_MAKE_FILE_))
include $(MAKEFILE_DIR)/Common.inc
Doesn't the manual give a recipe based on MAKEFILE_LIST?
Basically
this_makefile := $(lastword $(MAKEFILE_LIST))
before any include directives should do the trick.
Look at GNU make - Other Special Variables. MAKEFILE_LIST includes all Makefiles read. So, if you take the first one and extract the directory, you're done.
MAKEFILE_DIR=$(dir $(firstword $(MAKEFILE_LIST)))
include $(MAKEFILE_DIR)Common.inc
Directly related to this question. How can I make the include directive in makefiles behave relatively to the location of the current script?
Assume that the current path is arbitrary and you have no control over it. Only the makefile location is known. Your makefile is not the root one - it's included. That's exactly how it is in Android NDK.
Is there a builtin variable with the current makefile's name? Can I strip filename away from it, leaving just the path? Using make 3.81 on Cygwin.
You can get the name of the makefile being currently processed from MAKEFILE_LIST builtin variable.
Given that the current makefile is the last one that has been included (in other words you didn't use another include directive since the beginning of the current script), the path to the script itself would be:
SELF_DIR := $(dir $(lastword $(MAKEFILE_LIST)))
Now you are able to include a script in the same directory as such (note an absence of slash, it has already been added by $(dir ...)):
include $(SELF_DIR)another.mk
Note: In GNU Make 3.80 there was no lastword builtin function. In that case you may implement it as follows replacing $(lastword ...) with $(call lastword,...):
lastword = $(if $(firstword $1),$(word $(words $1),$1))
Is there a builtin variable with the current makefile's name?
Yes, there is, use ${CURDIR}. This is the directory where top-level Makefile is located, so you don't need to strip anything from it.
http://www.gnu.org/software/make/manual/make.html#Recursion
I find that relative paths work (GNUMake 3.81), but if they don't for you, try this:
include $(abspath ../whatever)