I am trying to create a vhdl code that will randomly blink four LEDs. After pushing a button that corresponds to the blinking led, a score will be displayed using 7 segment after 60 seconds.
Can anyone help me in generating random LED blink for the 4 LEDs?
Have a look at a Linear Feedback Shift Register. That'll give you a pseudo-random sequence of whatever length you want, and it's both effective and easy to implement in VHDL.
Depending on "how random" you need your sequence to be, you could for instance create a 16 bit long LFSR, and then use four arbitrarily selected bits from this to display (instead of using four consecutive bits, which might make the next value easier to guess, depending on the implementation).
Related
I'm working on a guitar effects "pedal" using the NEXSYS A7 Board.
For this purpose, I've purchased the I2S2 PMOD and successfully got it up and running using the example code provided by Digilent.
Currently, the design is a "pass-through", meaning that audio comes into the FPGA and immediately out.
I'm wondering what would be the correct way to store the data, make some DSP on this data to create the effects, and then transmit the modified data back to the I2S2 PMOD.
Maybe it's unnecessary to store the data?
maybe I can pass it through an RTL block that's responsible for applying the effect and then simply transmit the modified data out?
Collated from comments and extended.
For a live performance pedal you don't want to store much data; usually 10s of ms or less. Start with something simple : store 50 or 100ms of data in a ring (read old data, store new data, inc address modulo memory size). Output = Newdata = ( incoming sample * 0.n + olddata * (1 - 0.n)) for variable n. Very crude reverb or echo.
Yes, ring = ring buffer FIFO. And you'll see my description is a very crude implementation of a ring buffer FIFO.
Now extend it to separate read and write pointers. Now read and write at different, harmonically related rates ... you have a pitch changer. With glitches when the pointers cross.
Think of ways to hide the glitches, and soon you'll be able to make the crappy noises Autotune adds to most all modern music from that bloody Cher song onwards. (This takes serious DSP : something called interpolating filters is probably the simplest way. Live with the glitches for now)
btw if I'm interested in a distortion effect, can it be accomplished by simply multiplying the incoming data by a constant?
Multiplying by a constant is ... gain.
Multiplying a signal by itself is squaring it ... aka second harmonic distortion or 2HD (which produces components on the octave of each tone in the input).
Multiplying a signal by the 2HD is cubing it ... aka 3HD, producing components a perfect fifth above the octave.
Multiplying the 2HD by the 2HD is the fourth power ... aka 4HD, producing components 2 octaves higher, or a perfect fourth above that fifth.
Multiply the 4HD by the signal to produce 5HD ... and so on to probably the 7th. Also note that these components will decrease dramatically in level; you probably want to add gain beyond 2HD, multiply by 4 (= shift left 2 bits) as a starting point, and increase or decrease as desired.
Now multiply each of these by a variable gain and mix them (mixing is simple addition) to add as many distortion components you want as loud as you want ... don't forget to add in the original signal!
There are other approaches to adding distortion. Try simply saturating all signals above 0.25 to 0.25, and all signals below -0.25 to -0.25, aka clipping. Sounds nasty but mix a bit of this into the above, for a buzz.
Learn how to make white noise (pseudo-random number, usually from a LFSR).
Multiply this by the input signal, and mix or match with the above, for some fuzz.
Learn digital filtering (low pass, high pass, band pass for EQ), and how to control filters with noise or the input signal, the world of sound is open to you.
I am working on designing a mandelbrot viewer and I am designing hardware for squaring values. My squarer is recursively built where a 4bit squarer relies on 2, 2bit squarers. so for my 16 bit squarer, that has 2 8bits squarers, and each one of those has 2 4bit squarer's.
As you can see the recursivity begins to make the design blow up in complexity. To help speed up my design i would like to use a 4input ROM that emulates a 4bit squarer. So when you enter 3 in the rom, it outputs 9, when you enter 15, it outputs 225.
I know that a normal LUT implemented in a logic cell ay have 3 or 4 input variables and only 1 output, but i need an 8 bit output so I need more of a ROM then a LUT.
Any and all help is appreciated, Im curious how the FPGA will store those ROMs and if storing it in ROM would be faster than computing the 4input Square.
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Jarvi
To square a 4-bit number explicitly using LUTs, you would need to use 8 4-input LUTs. Each LUT's output would give you one bit of the 8-bit product.
The overall size and fmax performance of your design may be achieved with this approach, using larger block RAM primitives (as ROM), dedicated MAC (multiply-accumulate) units, or by using the normal mulitiplication operator * and relying on your synthesis tool's optimization.
You may also want to review some research papers related to this topic, for example here.
I've made an I2S transmitter to generate a "sound" out of my FPGA. The next step I would like to do, is create a sine. I've made 16 samples in a LUT. My question is how to implement something like this in VHDL. And also how you load the samples in sequence. Who has tried this already, and could share his knowledge?
I've made a Lookup table with 16 samples:
0 0π
0,382683432 1/16π
0,707106781 1/8π
0,923879533 3/16π
1 1/4π
0,923879533 5/16π
0,707106781 3/8π
0,382683432 7/16π
3,23114E-15 1π
-0,382683432 1 1/16π
-0,707106781 1 1/8π
-0,923879533 1 3/16π
-1 1 1/4π
-0,923879533 1 5/16π
-0,707106781 1 3/8π
-0,382683432 1 7/16π
-6,46228E-15 2π
The simplest solution is to make a ROM which is just a big case statement.
FPGA synthesis tools will map this on ore more LUT's.
Note that for bigger tables only 1/4 of the wave is stored, the other values are derived.
I would like to send out a 24 bit samples, do you also know how to do that with this data (binary!)?
24 bits (signed) mean you have to convert your floating point values to integer values in the range -8388608..8388607. (For symmetry reason you would use -8388608..8388607)
Thus multiply the sine values (which you know are in the range -1..1) with 8388607.
The frequency of the sine depends on how fast (many samples per second) you send.
I am doing a VLSI Project and I am implementing a Barrel Shifter using a tool called DSCH.The schematic for the same is realized using Transmission Gates.
What the circuit does is, it ROTATES the 8 bit word(8-bit shifter) with as many rotations chosen from a decoder in one clock cycle.
But I want to know the use of a rotator and why is it still called a shifter even though it's rotating.
Also please help me with some applications regarding Rotator which could be added to the present circuit to show it's use?
Rotation is just shifting with the bit exiting from one end fed back into the input at the other end, possibly by way of the carry flag bit. At the level of a simple implementation, it would make sense to have one circuit for both operations, with some additional control lines to select the source at the input side between the output of the other side, 0, or 1. Sign extension during right shift of 2's complement numbers would be another selectable option often built in.
The stackexchange sites aren't really suited to "list" questions including about applications, but a couple come to mind:
If you want a vector to test every bit of another value in turn, and to do so repeatedly, you could just keep rotating an initial one-bit-active value over an over, never having to re-initialize it.
You could swap a two-part (typically double-byte) value to imitate the opposite endieness of encoding by rotating it half way. Or putting it another way, it can be a single-operation swap of the values of two pairable but also independently accessible registers (think AL and AH together making up AX in real mode x86). But this will not work two endian swap a four-part value, such as a 32-bit value on a byte-addressable machine.
Various coding, checksum, and hashing schemes may wish to transform a value
I am trying to implement a 7-segment counter using VHDL.
The counter starts from 0 and increments an integer value to a max of 9999.
The value is passed to a bloc that is supposed to "split" the number into digits so that i can display them on the 7-segment which are multiplexed...
I have already done this on a PIC using many methods such as Interrupts... but now that i am trying to do this on a FPGA (Xilinx Spartan 3E Starter Board to be exact) i noticed while implementing the code i've wrote that i can't use neither division nor modulus because they cannot be implemented...
Edit: I know i could just map the values 0..9999 each alone but that is far far fetched.
Surely there is another way, but i can't think of it.
Any hint on a workaround would be very appreciated!
Well, if your number is in decimal, just extract the bits containing each digit and send them to your display multiplexor. The LSD is num[3:0], the MSD is num[15:12], etc.