I'm using DJGPP make under DOS.
This is my main Makefile:
BIN_DIR = bin
OBJ_DIR = obj
DIRS_FOR_CREATION = $(BIN_DIR) $(OBJ_DIR)
SOURCE_DIRS = argparse logger transmission tests
EXECUTABLE_NAME = $(notdir $(shell pwd))
EXECUTABLE_FILE = $(BIN_DIR)/$(EXECUTABLE_NAME)
CC = cc
CFLAGS =
INCLUDES =
LFLAGS =
LIBS =
MAIN_SOURCE = main.c
MAIN_OBJ = $(OBJ_DIR)/main.o
all: directories submodules main $(EXECUTABLE_FILE)
#echo $(EXECUTABLE_NAME) was compiled
directories:
mkdir -p $(DIRS_FOR_CREATION)
submodules:
$(MAKE) -C $(word 1, $(SOURCE_DIRS))
$(MAKE) -C $(word 2, $(SOURCE_DIRS))
$(MAKE) -C $(word 3, $(SOURCE_DIRS))
$(MAKE) -C $(word 4, $(SOURCE_DIRS))
main:
$(CC) $(CFLAGS) $(INCLUDES) -c $(MAIN_SOURCE) -o $(MAIN_OBJ)
$(EXECUTABLE_FILE): $(MAIN_SOURCE)
$(CC) $(CFLAGS) $(INCLUDES) -o $(EXECUTABLE_FILE) $(MAIN_OBJ) $(LFLAGS) $(LIBS)
And this is works perfectly on QNX, but in DOSBox I'm getting the following error:
makefile:19: *** multiple target patterns. Stop.
19 line is all: directories submodules main $(EXECUTABLE_FILE). What should I do to fix this?
You should add:
$(info EXECUTABLE_NAME = '$(EXECUTABLE_NAME)')
$(info EXECUTABLE_FILE = '$(EXECUTABLE_FILE)')
so you can see what that variable contains. My suspicion is that it contains a colon (:) which is special to make.
Related
I'm trying to get my Makefile to compile only changed source files. In the Makefile below, I would like the targets: %.o : ${SOURCE_DIR}/%.c and %.o : ${SOURCE_DIR}/%.s to only compile if the source file has changed, or the corresponding .o object file does not exist.
Not entirely sure what's wrong here, can someone please offer some advice?
# Project name
# ---------------------------------------------------------------------------------------------------------------------
PROJECT_NAME = stm32f4_template
# Source configuration
# ---------------------------------------------------------------------------------------------------------------------
OUT_DIR = ./Build
SOURCE_DIR = ./Src
SOURCES = main.c
SOURCES += startup.s
C_SOURCES = $(filter %.c, $(SOURCES))
ASM_SOURCES += $(filter %.s, $(SOURCES))
OBJECTS = $(C_SOURCES:.c=.o)
OBJECTS += $(ASM_SOURCES:.s=.o)
# Tools
# ---------------------------------------------------------------------------------------------------------------------
CC = arm-none-eabi-gcc
LD = arm-none-eabi-ld -v
CP = arm-none-eabi-objcopy
OD = arm-none-eabi-objdump
# Compilation, linker and other tool flags
# ---------------------------------------------------------------------------------------------------------------------
CFLAGS = -I./ -c -fno-common -O0 -g -mcpu=cortex-m4 -mthumb
LFLAGS = -nostartfiles -TLinker/memory.ld -TLinker/sections.ld
CPFLAGS = -Obinary
ODFLAGS = -S
# Target: all ---------------------------------------------------------------------------------------------------------
#
all: setup $(PROJECT_NAME).elf
#echo "Done! $?"
# Target: setup -------------------------------------------------------------------------------------------------------
#
setup:
#mkdir -p $(OUT_DIR)
# Target: $(PROJECT_NAME).elf
# ---------------------------------------------------------------------------------------------------------------------
$(PROJECT_NAME).elf: $(OBJECTS)
#echo "Linking $#"
$(LD) $(LFLAGS) -o ${OUT_DIR}/main.elf $(OUT_DIR)/main.o
#echo
# Target %.o (.c sources)
# ---------------------------------------------------------------------------------------------------------------------
%.o : ${SOURCE_DIR}/%.c # --> Execute only if source changed!!!
#echo "Compiling $<"
$(CC) $(CFLAGS) $< -o $(OUT_DIR)/$#
#echo
# Target %.o (.s sources)
# ---------------------------------------------------------------------------------------------------------------------
%.o : ${SOURCE_DIR}/%.s # --> Execute only if source changed!!!
#echo "Compiling $<"
$(CC) $(CFLAGS) $< -o $(OUT_DIR)/$#
#echo
# Target: clean
# ---------------------------------------------------------------------------------------------------------------------
clean:
#echo "Cleaning build output..."
#rm -rf $(OUT_DIR)
This rule:
%.o : ${SOURCE_DIR}/%.c # --> Execute only if source changed!!!
#echo "Compiling $<"
$(CC) $(CFLAGS) $< -o $(OUT_DIR)/$#
The problem is that the target of this rule is main.o, so Make uses it in an attempt to build main.o, because another target demands main.o, but what this rule actually builds is Build/main.o. Make keeps running this rule because it sees that main.o isn't there (and the rule for the elf file uses Build/main.o, which Make keeps rebuilding unawares).
I suggest you change it:
OBJECTS = $(patsubst %.c, $(OUT_DIR)/%.o, $(C_SOURCES))
$(OUT_DIR)/%.o : ${SOURCE_DIR}/%.c # --> this should work
#echo "Compiling $<"
$(CC) $(CFLAGS) $< -o $#
The same goes for the other %.o rule.
CC = g++49
#General Flags
CFLAGS =
#debug flags
CFLAGS +=
#Target Liker Flags
CFLAGS +=
TARGET = ../game
INCDIR += -I
LIBDIR += -L
LIBS += -l
##############################################
INCDIR += -I
LIBDIR += -L
LIBS += -l
##############################################
CPP_FILE =
OBJDIR =../../Object's
CPPOBJS = $(CPP_FILE:%.cpp=$(OBJDIR)/%.o)
default: $(TARGET)
$(OBJDIR)/%.o: %.cpp
#echo compile $<
#$(CC) $(CFLAGS) $(INCDIR) -c $< -o $#
$(TARGET): $(CPPOBJS)
#echo linking....
#$(CC) $(CFLAGS) $(LIBDIR) $(CPPOBJS) $(LIBS) -o $(TARGET)
Soo this si my makefile .
I want to find all .cpp files and compile.
Without their full name specified in CPP_FILE
Example :
CPP_FILE : test.cpp main.cpp slow.cpp scan.cpp
I want something like CPP_FILE = *.cpp
It is this possible?
Make provides a wildcard function for this very purpose.
CPP_FILE = $(wildcard my_dir/*.cpp)
I am adapting my Makefile to look into 4 directories, rather than 2 (it had one for source files and one for header files, but I've added a new folder for common source and include). I have something like follows:
CC = g++
FLAGS = -g -c
BUILDDIR = build
INCLUDEDIR = -Icode/inc -I../common/code/inc -I/usr/include/libxml2
SOURCEDIR = code/src ../common/code/src
SOURCES = $(wildcard $(SOURCEDIR)/*.cpp)
OBJECTS = $(patsubst $(SOURCEDIR)/%.cpp,$(BUILDDIR)/%.o,$(SOURCES))
EXECUTABLE = Exec
all: $(BUILDDIR)/$(EXECUTABLE)
$(BUILDDIR)/$(EXECUTABLE): $(OBJECTS)
$(CC) $^ -o $# -lpthread -lxml2
$(OBJECTS): $(BUILDDIR)/%.o : $(SOURCEDIR)/%.cpp
$(CC) $(FLAGS) $< $(INCLUDEDIR) -o $# -Wno-write-strings
I tried to add one entry to INCLUDEDIR as follows:
-I../common/code/inc
And added ../common/code/src to SOURCEDIR:
SOURCEDIR = code/src ../common/code/src
This is not currently working and I am wondering how to fix it please. I am getting the error:
Makefile:27: target `code/src' doesn't match the target pattern
but I cannot find how to fix it so far. Any help would be appreciated.
EDIT: After following MadScientist response below, I am getting the following output:
g++ -c -o code/src/Client.o code/src/Client.cpp
code/src/Client.cpp:1:20: fatal error: Client.h: No such file or directory
compilation terminated.
make: *** [code/src/Client.o] Error 1
Updated Makefile:
SOURCEDIR = code/src ../common/code/src
SOURCES = $(wildcard $(addsuffix /*.cpp,$(SOURCEDIR)))
OBJECTS = $(SOURCES:%.cpp=%.o)
$(BUILDDIR)/$(EXECUTABLE): $(OBJECTS)
$(CC) $^ -o $# -lpthread -lxml2
$(BUILDDIR)/%.o : ../common/code/src/%.cpp
$(CC) $(FLAGS) $< $(INCLUDEDIR) -o $# -Wno-write-strings
$(BUILDDIR)/%.o : code/src/%.cpp
$(CC) $(FLAGS) $< $(INCLUDEDIR) -o $# -Wno-write-strings
PS:
I was able to fix it using the following:
SOURCEDIR = code/src ../common/code/src
SOURCES = $(wildcard $(addsuffix /*.cpp,$(SOURCEDIR)))
TEMP_OBJ = $(SOURCES:%.cpp=%.o)
NOT_DIR = $(notdir $(TEMP_OBJ))
OBJECTS = $(addprefix $(BUILDDIR)/, $(NOT_DIR))
Sure, because now your static pattern rule expands to:
$(OBJECTS): build/%.o : code/src ../common/code/src/%.cpp
which is illegal syntax. If you avoid using static pattern rules, and instead use pattern rules, then it will just work. Replace your single static pattern rule with two pattern rules:
$(BUILDDIR)/%.o : code/src/%.cpp
$(CC) $(FLAGS) $< $(INCLUDEDIR) -o $# -Wno-write-strings
$(BUILDDIR)/%.o : ../common/code/src/%.cpp
$(CC) $(FLAGS) $< $(INCLUDEDIR) -o $# -Wno-write-strings
EDIT: you also need to change other uses of SOURCEDIR:
SOURCES = $(wildcard $(addsuffix /*.cpp,$(SOURCEDIR))
OBJECTS = $(patsubst %.cpp,$(BUILDDIR)/%.o,$(notdir $(SOURCES)))
I am working on programming a nrf51822 evaluation board(This one). I have been looking at this site to program it and have gotten the blinking program to work.
I want to modify the makefile provided on the site previously mentioned, such that when I go along I pretty much only have to add to the list of files to compile. Below is what I have been trying to get to work, but I am not very good with makefiles.
CC := /opt/arm-2012.09/bin/arm-none-eabi-gcc
OBJCOPY := /opt/arm-2012.09/bin/arm-none-eabi-objcopy
NRF51_SDK := /opt/nrf51sdk
NRF51_INCLUDE := $(NRF51_SDK)/Nordic/nrf51822/Include
NRF51_SRC := $(NRF51_SDK)/Nordic/nrf51822/Source
CPU := cortex-m0
BOARD := BOARD_PCA10001
OBJDIR = .
OBJDIR += $(SRC)/templates/
INCLUDEDIRS = $(NRF51_INCLUDE)
INCLUDEDIRS += $(NRF51_INCLUDE)/gcc
DEFINE = BOARD_PCA10001
DEFINE += NRF51
CFLAGS = -mcpu=$(CPU)
CFLAGS +=-mthumb
CFLAGS += $(patsubst %,-D%, $(DEFINE))
CFLAGS += $(patsubst %,-I%, $(INCLUDEDIRS))
CFLAGS += -c
SRC = main.c
SRC += $(NRF51_SRC)/templates/system_nrf51.c
SRC += $(NRF51_SRC)/nrf_delay/nrf_delay.c
ASSEMBLY_SRC += $(NRF51_SRC)/templates/gcc/gcc_startup_nrf51.s
all: main.bin main.hex
%.o : %.c
#echo "Compiling: " $<
$(CC) $(CFLAGS) $<
%.o : %.s
#echo "Compiling: " $<
$(CC) $(CFLAGS) $<
main.out: $(SRC) $(ASSEMBLY_SRC)
$(CC) -L"/opt/arm-2012.09/arm-none-eabi/lib/armv6-m" -L"/opt/arm-2012.09/lib/gcc/arm-none-eabi/4.7.2/armv6-m" -Xlinker -Map=main.map -mcpu=$(CPU) -mthumb -mabi=aapcs -T$(NRF51_SDK)/Nordic/nrf51822/Source/templates/gcc/gcc_linker_script_nrf51.ld main.o system_nrf51.o nrf_delay.o gcc_startup_nrf51.o -o main.out
main.bin: main.out
$(OBJCOPY) -O binary main.out main.bin
main.hex: main.out
$(OBJCOPY) -O ihex main.out main.hex
install: main.bin
sed 's#\[\[--filename--\]\]#$(PWD)/main.bin#' segger/burn-template.seg > burn.seg
./segger/segger.sh $(PWD)/burn.seg
clean:
rm *.o *.out *.hex *.seg *.map *.bin *.hex
When it runs make it just outputs the following:
/opt/arm-2012.09/bin/arm-none-eabi-gcc -L"/opt/arm-2012.09/arm-none-eabi/lib/armv6-m" -L"/opt/arm-2012.09/lib/gcc/arm-none-eabi/4.7.2/armv6-m" -Xlinker -Map=main.map -mcpu=cortex-m0 -mthumb -mabi=aapcs -T/opt/nrf51sdk/Nordic/nrf51822/Source/templates/gcc/gcc_linker_script_nrf51.ld main.o system_nrf51.o nrf_delay.o gcc_startup_nrf51.o -o main.out
arm-none-eabi-gcc: error: main.o: No such file or directory
arm-none-eabi-gcc: error: system_nrf51.o: No such file or directory
arm-none-eabi-gcc: error: nrf_delay.o: No such file or directory
arm-none-eabi-gcc: error: gcc_startup_nrf51.o: No such file or directory
make: *** [main.out] Error 1
Is there anyone around here that can help me with this?
(Copied answer from OP Edit to Solution)
The OP Wrote:
I just figured it out, and am sharing it if anyone wants to know how I did it. Also if anyone would like to comment on how to make it 'better'
CC := /opt/arm-2012.09/bin/arm-none-eabi-gcc
OBJCOPY := /opt/arm-2012.09/bin/arm-none-eabi-objcopy
NRF51_SDK := /opt/nrf51sdk
NRF51_INCLUDE := $(NRF51_SDK)/Nordic/nrf51822/Include
NRF51_SRC := $(NRF51_SDK)/Nordic/nrf51822/Source
CPU := cortex-m0
BOARD := BOARD_PCA10001
INCLUDEDIRS = $(NRF51_INCLUDE)
INCLUDEDIRS += $(NRF51_INCLUDE)/gcc
DEFINE = BOARD_PCA10001
DEFINE += NRF51
# For the compiler stage
CFLAGS = -mcpu=$(CPU)
CFLAGS += -mthumb
CFLAGS += $(patsubst %,-D%, $(DEFINE))
CFLAGS += $(patsubst %,-I%, $(INCLUDEDIRS))
CFLAGS += -Wall
# For the Linker stage
LDIRS = /opt/arm-2012.09/arm-none-eabi/lib/armv6-m
LDIRS += /opt/arm-2012.09/lib/gcc/arm-none-eabi/4.7.2/armv6-m
TDIRS = $(NRF51_SRC)/templates/gcc/gcc_linker_script_nrf51.ld
LFLAGS = -mcpu=$(CPU)
LFLAGS += -mthumb
LFLAGS += -mabi=aapcs
LFLAGS += -Wall
LFLAGS += $(patsubst %, -L%, $(LDIRS))
LFLAGS += $(patsubst %, -T%, $(TDIRS))
# Source files to compile
SRC = main.c
SRC += $(NRF51_SRC)/templates/system_nrf51.c
SRC += $(NRF51_SRC)/nrf_delay/nrf_delay.c
ASSEMBLY_SRC += $(NRF51_SRC)/templates/gcc/gcc_startup_nrf51.s
OBJ = $(SRC:.c=.o) $(ASSEMBLY_SRC:.s=.o)
# Default target
all: begin gcc_version build end
build: main.bin main.hex
main.out: $(OBJ)
#echo
#echo "Linking compiled file. Output will be saved to: " $#
$(CC) $(LFLAGS) $(notdir $(OBJ)) -o $#
main.bin: main.out
#echo
#echo "Making binary file. Output will be saved to: " $#
$(OBJCOPY) -O binary main.out main.bin
main.hex: main.out
#echo
#echo "Making hex file. Output will be saved to: " $#
$(OBJCOPY) -O ihex main.out main.hex
upload: all
#echo
#echo "Uploading file to MCU: "
sed 's#\[\[--filename--\]\]#$(PWD)/main.bin#' segger/burn-template.seg > burn.seg
./segger/segger.sh $(PWD)/burn.seg
clean:
rm *.o *.out *.hex *.seg *.map *.bin *.hex
# Eye Candy
begin:
#echo
#echo "---------- begin ----------"
end:
#echo
#echo "----------- end -----------"
gcc_version:
#echo
#$(CC) --version
# General Rule for compiling C source files
%.o : %.c
#echo
#echo "Compiling: " $(notdir $<)
$(CC) $(CFLAGS) -c $< -o $(notdir $#)
# General Rule for compiling assembly source files
%.o : %.s
#echo
#echo "Compiling: " $(notdir $<)
$(CC) $(CFLAGS) -c $< -o $(notdir $#)
This at least works for now :)
I have to create different *.o files from a same set of *.c using various CFLAGS. I wanted to use patsubst to generate different *.o files from same *.c. I am doing something wrong the following statement, please help (I want to generate one set of object files having ($<)_O0.o and the other ($<)_O2.o from the same set of c source files):
$(CC) $(CFLAGS_02) -c $< -o $(patsubst %.c,%_O2.o,$<)
Thanks
Use patsubst to make lists of the objects that you want to build, and then use separate rules for each type of build.
Something like this:
SRC_FILES = source1.c source2.c
OBJ_FILES_O0 = $(patsubst %.c,%_O0.o,$(SRC_FILES))
OBJ_FILES_O2 = $(patsubst %.c,%_O2.o,$(SRC_FILES))
CFLAGS_O0 := -O0
CFLAGS_O2 := -O2
all: $(OBJ_FILES_O0) $(OBJ_FILES_O2)
$(OBJ_FILES_O0): %_O0.o: %.c
$(CC) $(CFLAGS_O0) -c $< -o $#
$(OBJ_FILES_O2): %_O2.o: %.c
$(CC) $(CFLAGS_O2) -c $< -o $#
You can also use wild cards to specify all files in the directory.
eg:
#Generic Makefile.
CC := g++
LD := g++
CFLAGS := -c
LDFLAGS := -L<path to lib> -l<libname> \
-L<path to lib> -l>libname> \
......................
ifeq (${TARGETARCH}, debug)
CFLAGS += -g -O0
elif
CFLAGS += -O4 -DNDEBUG
SRCFILES := $(wildcard *.cpp)
OBJFILES := $(patsubst %.cpp, %.o, ${SRCFILES})
all: main
main: ${OBJFILES}
#echo "[Linking]"$#
${LD} ${LDFLAGS} ${OBJFILES}
%.o: %.cpp
#echo "[Compiling]"$#
${CC} ${CFLAGS} $^ -o $#