patsubst on makefile - makefile

I have to create different *.o files from a same set of *.c using various CFLAGS. I wanted to use patsubst to generate different *.o files from same *.c. I am doing something wrong the following statement, please help (I want to generate one set of object files having ($<)_O0.o and the other ($<)_O2.o from the same set of c source files):
$(CC) $(CFLAGS_02) -c $< -o $(patsubst %.c,%_O2.o,$<)
Thanks

Use patsubst to make lists of the objects that you want to build, and then use separate rules for each type of build.
Something like this:
SRC_FILES = source1.c source2.c
OBJ_FILES_O0 = $(patsubst %.c,%_O0.o,$(SRC_FILES))
OBJ_FILES_O2 = $(patsubst %.c,%_O2.o,$(SRC_FILES))
CFLAGS_O0 := -O0
CFLAGS_O2 := -O2
all: $(OBJ_FILES_O0) $(OBJ_FILES_O2)
$(OBJ_FILES_O0): %_O0.o: %.c
$(CC) $(CFLAGS_O0) -c $< -o $#
$(OBJ_FILES_O2): %_O2.o: %.c
$(CC) $(CFLAGS_O2) -c $< -o $#

You can also use wild cards to specify all files in the directory.
eg:
#Generic Makefile.
CC := g++
LD := g++
CFLAGS := -c
LDFLAGS := -L<path to lib> -l<libname> \
-L<path to lib> -l>libname> \
......................
ifeq (${TARGETARCH}, debug)
CFLAGS += -g -O0
elif
CFLAGS += -O4 -DNDEBUG
SRCFILES := $(wildcard *.cpp)
OBJFILES := $(patsubst %.cpp, %.o, ${SRCFILES})
all: main
main: ${OBJFILES}
#echo "[Linking]"$#
${LD} ${LDFLAGS} ${OBJFILES}
%.o: %.cpp
#echo "[Compiling]"$#
${CC} ${CFLAGS} $^ -o $#

Related

GNU Make correct behaviour when including other makefiles

I have the following makefile in the root of the project:
Makefile
# Board version
# Available: 3
PI ?= 3
# Kernel binaries
ifeq ($(PI), 3)
KERNEL_IMG := kernel8.img
else ifeq ($(PI), 2)
KERNEL_IMG := kernel7.img
else ifeq ($(PI), 1)
KERNEL_IMG := kernel.img
else
$(error Unsupported Raspberry Pi version)
endif
KERNEL_ELF := $(patsubst %.img,%.elf,$(KERNEL_IMG))
# Directories/paths
BUILD_DIR := build
# Toolchain
TOOLCHAIN ?= aarch64-elf
OBJCOPY := $(TOOLCHAIN)-objcopy
LD := $(TOOLCHAIN)-ld
CC := $(TOOLCHAIN)-gcc
# Misc
LINKER_SCRIPT := linker.ld
# Flags
LDFLAGS := -T $(LINKER_SCRIPT)
ASFLAGS :=
CFLAGS :=
# Source files
C_SRC := $(wildcard *.c)
ASM_SRC := $(wildcard *.S)
# Include
include pi/$(PI)/mod.mk
# Object files
OBJECTS := $(patsubst %,$(BUILD_DIR)/%.o,$(C_SRC))
OBJECTS += $(patsubst %,$(BUILD_DIR)/%.o,$(ASM_SRC))
# Targets
.PHONY: all builddirs clean
all: $(BUILD_DIR)/$(KERNEL_IMG)
$(BUILD_DIR)/$(KERNEL_IMG): $(BUILD_DIR)/$(KERNEL_ELF)
$(OBJCOPY) $< -O binary $#
$(BUILD_DIR)/$(KERNEL_ELF): $(LINKER_SCRIPT) $(OBJECTS)
$(LD) $(OBJECTS) $(LDFLAGS) -o $#
$(OBJECTS): | builddirs
builddirs: $(BUILD_DIR)/pi/$(PI)
$(BUILD_DIR)/pi/$(PI):
mkdir -p $#
$(BUILD_DIR)/%.S.o: %.S
$(CC) -c $< $(ASFLAGS) -o $#
$(BUILD_DIR)/%.c.o: %.c
$(CC) -c $< $(CFLAGS) -o $#
clean:
$(RM) -r $(BUILD_DIR)
It includes pi/3/mod.mk
C_SRC +=
ASM_SRC += pi/3/start.S
$(BUILD_DIR)/pi/3/start.S.o: pi/3/start.S pi/3/include/cpu/sysregs.h
$(CC) -c $< $(ASFLAGS) -o $#
Now here's the problem: whenever I run 'make' in the root of a project, '$(BUILD_DIR)/pi/3/start.S.o' rule invokes, instead of 'all'. If I move 'include pi/$(PI)/mod.mk' to the very bottom of the root makefile, and replace 'C_SRC' and 'ASM_SRC' variables in 'pi/3/mod.mk' with 'OBJECTS += $(BUILD_DIR)/pi/3/start.S.o' and invoke 'make', this rule isn't even invoked, so I get an error that make doesn't know how to build start.S.o.
What am I doing wrong and what is the best way to handle this?
Make's default goal is the first target in your Makefile. In your case the first target is the one defined in the included Makefile: $(BUILD_DIR)/pi/3/start.S.o. Either invoke make all or move the all rule in your Makefile such that it becomes the first one, or tell make that the default goal is all:
.DEFAULT_GOAL := all
(see GNU make manual).

Makefile : include in loop / loop outside targets

In my makefile I want to include some other makefile depending on a variable in a for loop, Is it possible.
Top Makefile :
CC = gcc
CFLAGS = -O0 -g3 -W -Wall -pedantic
LDFLAGS =
DEFINES =
PROJECT = proj
INCLUDES =
SOURCES =
TEMP_PATH := $(PROJECT)
include $(TEMP_PATH)/Makefile
$(for blocks in $(BLOCKS); do \
include $$(blocks)/Makefile; \
done)
all : $(PROJECT).exe
$(PROJECT).exe :
$(CC) $(CFLAGS) $(LDFLAGS) $(DEFINES) $(INCLUDES) $(SOURCES) -o $#
clean :
rm -rf *.exe
proj/Makefile :
CC = gcc
CFLAGS = -O0 -g3 -W -Wall -pedantic
LDFLAGS =
DEFINES =
BLOCKS := std_communication
INCLUDES := $(INCLUDES) -I $(TEMP_PATH)/Utils
INCLUDES := $(INCLUDES) -I $(TEMP_PATH)/Communication
SOURCES := $(SOURCES) $(wildcard $(TEMP_PATH)/Utils/*.c)
SOURCES := $(SOURCES) $(wildcard $(TEMP_PATH)/Communication/*.c)
SOURCES := $(SOURCES) $(wildcard $(TEMP_PATH)/main.c)
The for loop syntax seems to be wrong outside of loop.
You cannot write it like that, but you can just write:
include $(addsuffix /Makefile,$(BLOCKS))

Makefile: Adding 2nd directory for .h and .cpp files

I am adapting my Makefile to look into 4 directories, rather than 2 (it had one for source files and one for header files, but I've added a new folder for common source and include). I have something like follows:
CC = g++
FLAGS = -g -c
BUILDDIR = build
INCLUDEDIR = -Icode/inc -I../common/code/inc -I/usr/include/libxml2
SOURCEDIR = code/src ../common/code/src
SOURCES = $(wildcard $(SOURCEDIR)/*.cpp)
OBJECTS = $(patsubst $(SOURCEDIR)/%.cpp,$(BUILDDIR)/%.o,$(SOURCES))
EXECUTABLE = Exec
all: $(BUILDDIR)/$(EXECUTABLE)
$(BUILDDIR)/$(EXECUTABLE): $(OBJECTS)
$(CC) $^ -o $# -lpthread -lxml2
$(OBJECTS): $(BUILDDIR)/%.o : $(SOURCEDIR)/%.cpp
$(CC) $(FLAGS) $< $(INCLUDEDIR) -o $# -Wno-write-strings
I tried to add one entry to INCLUDEDIR as follows:
-I../common/code/inc
And added ../common/code/src to SOURCEDIR:
SOURCEDIR = code/src ../common/code/src
This is not currently working and I am wondering how to fix it please. I am getting the error:
Makefile:27: target `code/src' doesn't match the target pattern
but I cannot find how to fix it so far. Any help would be appreciated.
EDIT: After following MadScientist response below, I am getting the following output:
g++ -c -o code/src/Client.o code/src/Client.cpp
code/src/Client.cpp:1:20: fatal error: Client.h: No such file or directory
compilation terminated.
make: *** [code/src/Client.o] Error 1
Updated Makefile:
SOURCEDIR = code/src ../common/code/src
SOURCES = $(wildcard $(addsuffix /*.cpp,$(SOURCEDIR)))
OBJECTS = $(SOURCES:%.cpp=%.o)
$(BUILDDIR)/$(EXECUTABLE): $(OBJECTS)
$(CC) $^ -o $# -lpthread -lxml2
$(BUILDDIR)/%.o : ../common/code/src/%.cpp
$(CC) $(FLAGS) $< $(INCLUDEDIR) -o $# -Wno-write-strings
$(BUILDDIR)/%.o : code/src/%.cpp
$(CC) $(FLAGS) $< $(INCLUDEDIR) -o $# -Wno-write-strings
PS:
I was able to fix it using the following:
SOURCEDIR = code/src ../common/code/src
SOURCES = $(wildcard $(addsuffix /*.cpp,$(SOURCEDIR)))
TEMP_OBJ = $(SOURCES:%.cpp=%.o)
NOT_DIR = $(notdir $(TEMP_OBJ))
OBJECTS = $(addprefix $(BUILDDIR)/, $(NOT_DIR))
Sure, because now your static pattern rule expands to:
$(OBJECTS): build/%.o : code/src ../common/code/src/%.cpp
which is illegal syntax. If you avoid using static pattern rules, and instead use pattern rules, then it will just work. Replace your single static pattern rule with two pattern rules:
$(BUILDDIR)/%.o : code/src/%.cpp
$(CC) $(FLAGS) $< $(INCLUDEDIR) -o $# -Wno-write-strings
$(BUILDDIR)/%.o : ../common/code/src/%.cpp
$(CC) $(FLAGS) $< $(INCLUDEDIR) -o $# -Wno-write-strings
EDIT: you also need to change other uses of SOURCEDIR:
SOURCES = $(wildcard $(addsuffix /*.cpp,$(SOURCEDIR))
OBJECTS = $(patsubst %.cpp,$(BUILDDIR)/%.o,$(notdir $(SOURCES)))

Makefile for nrf51sdk

I am working on programming a nrf51822 evaluation board(This one). I have been looking at this site to program it and have gotten the blinking program to work.
I want to modify the makefile provided on the site previously mentioned, such that when I go along I pretty much only have to add to the list of files to compile. Below is what I have been trying to get to work, but I am not very good with makefiles.
CC := /opt/arm-2012.09/bin/arm-none-eabi-gcc
OBJCOPY := /opt/arm-2012.09/bin/arm-none-eabi-objcopy
NRF51_SDK := /opt/nrf51sdk
NRF51_INCLUDE := $(NRF51_SDK)/Nordic/nrf51822/Include
NRF51_SRC := $(NRF51_SDK)/Nordic/nrf51822/Source
CPU := cortex-m0
BOARD := BOARD_PCA10001
OBJDIR = .
OBJDIR += $(SRC)/templates/
INCLUDEDIRS = $(NRF51_INCLUDE)
INCLUDEDIRS += $(NRF51_INCLUDE)/gcc
DEFINE = BOARD_PCA10001
DEFINE += NRF51
CFLAGS = -mcpu=$(CPU)
CFLAGS +=-mthumb
CFLAGS += $(patsubst %,-D%, $(DEFINE))
CFLAGS += $(patsubst %,-I%, $(INCLUDEDIRS))
CFLAGS += -c
SRC = main.c
SRC += $(NRF51_SRC)/templates/system_nrf51.c
SRC += $(NRF51_SRC)/nrf_delay/nrf_delay.c
ASSEMBLY_SRC += $(NRF51_SRC)/templates/gcc/gcc_startup_nrf51.s
all: main.bin main.hex
%.o : %.c
#echo "Compiling: " $<
$(CC) $(CFLAGS) $<
%.o : %.s
#echo "Compiling: " $<
$(CC) $(CFLAGS) $<
main.out: $(SRC) $(ASSEMBLY_SRC)
$(CC) -L"/opt/arm-2012.09/arm-none-eabi/lib/armv6-m" -L"/opt/arm-2012.09/lib/gcc/arm-none-eabi/4.7.2/armv6-m" -Xlinker -Map=main.map -mcpu=$(CPU) -mthumb -mabi=aapcs -T$(NRF51_SDK)/Nordic/nrf51822/Source/templates/gcc/gcc_linker_script_nrf51.ld main.o system_nrf51.o nrf_delay.o gcc_startup_nrf51.o -o main.out
main.bin: main.out
$(OBJCOPY) -O binary main.out main.bin
main.hex: main.out
$(OBJCOPY) -O ihex main.out main.hex
install: main.bin
sed 's#\[\[--filename--\]\]#$(PWD)/main.bin#' segger/burn-template.seg > burn.seg
./segger/segger.sh $(PWD)/burn.seg
clean:
rm *.o *.out *.hex *.seg *.map *.bin *.hex
When it runs make it just outputs the following:
/opt/arm-2012.09/bin/arm-none-eabi-gcc -L"/opt/arm-2012.09/arm-none-eabi/lib/armv6-m" -L"/opt/arm-2012.09/lib/gcc/arm-none-eabi/4.7.2/armv6-m" -Xlinker -Map=main.map -mcpu=cortex-m0 -mthumb -mabi=aapcs -T/opt/nrf51sdk/Nordic/nrf51822/Source/templates/gcc/gcc_linker_script_nrf51.ld main.o system_nrf51.o nrf_delay.o gcc_startup_nrf51.o -o main.out
arm-none-eabi-gcc: error: main.o: No such file or directory
arm-none-eabi-gcc: error: system_nrf51.o: No such file or directory
arm-none-eabi-gcc: error: nrf_delay.o: No such file or directory
arm-none-eabi-gcc: error: gcc_startup_nrf51.o: No such file or directory
make: *** [main.out] Error 1
Is there anyone around here that can help me with this?
(Copied answer from OP Edit to Solution)
The OP Wrote:
I just figured it out, and am sharing it if anyone wants to know how I did it. Also if anyone would like to comment on how to make it 'better'
CC := /opt/arm-2012.09/bin/arm-none-eabi-gcc
OBJCOPY := /opt/arm-2012.09/bin/arm-none-eabi-objcopy
NRF51_SDK := /opt/nrf51sdk
NRF51_INCLUDE := $(NRF51_SDK)/Nordic/nrf51822/Include
NRF51_SRC := $(NRF51_SDK)/Nordic/nrf51822/Source
CPU := cortex-m0
BOARD := BOARD_PCA10001
INCLUDEDIRS = $(NRF51_INCLUDE)
INCLUDEDIRS += $(NRF51_INCLUDE)/gcc
DEFINE = BOARD_PCA10001
DEFINE += NRF51
# For the compiler stage
CFLAGS = -mcpu=$(CPU)
CFLAGS += -mthumb
CFLAGS += $(patsubst %,-D%, $(DEFINE))
CFLAGS += $(patsubst %,-I%, $(INCLUDEDIRS))
CFLAGS += -Wall
# For the Linker stage
LDIRS = /opt/arm-2012.09/arm-none-eabi/lib/armv6-m
LDIRS += /opt/arm-2012.09/lib/gcc/arm-none-eabi/4.7.2/armv6-m
TDIRS = $(NRF51_SRC)/templates/gcc/gcc_linker_script_nrf51.ld
LFLAGS = -mcpu=$(CPU)
LFLAGS += -mthumb
LFLAGS += -mabi=aapcs
LFLAGS += -Wall
LFLAGS += $(patsubst %, -L%, $(LDIRS))
LFLAGS += $(patsubst %, -T%, $(TDIRS))
# Source files to compile
SRC = main.c
SRC += $(NRF51_SRC)/templates/system_nrf51.c
SRC += $(NRF51_SRC)/nrf_delay/nrf_delay.c
ASSEMBLY_SRC += $(NRF51_SRC)/templates/gcc/gcc_startup_nrf51.s
OBJ = $(SRC:.c=.o) $(ASSEMBLY_SRC:.s=.o)
# Default target
all: begin gcc_version build end
build: main.bin main.hex
main.out: $(OBJ)
#echo
#echo "Linking compiled file. Output will be saved to: " $#
$(CC) $(LFLAGS) $(notdir $(OBJ)) -o $#
main.bin: main.out
#echo
#echo "Making binary file. Output will be saved to: " $#
$(OBJCOPY) -O binary main.out main.bin
main.hex: main.out
#echo
#echo "Making hex file. Output will be saved to: " $#
$(OBJCOPY) -O ihex main.out main.hex
upload: all
#echo
#echo "Uploading file to MCU: "
sed 's#\[\[--filename--\]\]#$(PWD)/main.bin#' segger/burn-template.seg > burn.seg
./segger/segger.sh $(PWD)/burn.seg
clean:
rm *.o *.out *.hex *.seg *.map *.bin *.hex
# Eye Candy
begin:
#echo
#echo "---------- begin ----------"
end:
#echo
#echo "----------- end -----------"
gcc_version:
#echo
#$(CC) --version
# General Rule for compiling C source files
%.o : %.c
#echo
#echo "Compiling: " $(notdir $<)
$(CC) $(CFLAGS) -c $< -o $(notdir $#)
# General Rule for compiling assembly source files
%.o : %.s
#echo
#echo "Compiling: " $(notdir $<)
$(CC) $(CFLAGS) -c $< -o $(notdir $#)
This at least works for now :)

Makefile which can generate all object files in a specific path

Somewhere I am going wrong !!
I am trying to generate the object files in ../bin/
But the below code generates in corresponding source file directory.
Below the code, which I am running.
Modified code:
LIB = $(BIN_DIR)/libutils.a
APP = $(BIN_DIR)/app
CC = gcc
AR = ar
CFLAGS = -Wall -g
LDFLAGS =
all: $(LIB) $(APP)
SRC = $(SRC_DIR)/add.c \
$(SRC_DIR)/sub.c
OBJ = $(SRC:.c=.o)
INCLUDES = -I$(INC_DIR)/
LIBS = -L../ -L/usr/local/lib -lm
LDFLAGS = -g
.SUFFIXES: .c
.c.o:
$(CC) $(INCLUDES) -c $(SRC_DIR)/$< -o $(BIN_DIR)/$#
$(LIB): $(OBJ)
$(AR) rcs $(LIB) $(OBJ)
$(BIN_DIR)/app: $(BIN_DIR)/test.o \
$(BIN_DIR)/t.o \
$(BIN_DIR)/libutils.a
$(CC) $(LDFLAGS) -o $# $^
clean:
rm -f $(LIB) $(BIN_DIR)/* $(SRC_DIR)/*.o *.o
Thank you :)
You still have the rule:
$(LIB): $(OBJ)
...
and OBJ is still src_dir/add.o src_dir/sub.o, so that's where Make will try to build these objects if your object rule works as intended. So, first step:
SRC = $(SRC_DIR)/add.c \
$(SRC_DIR)/sub.c
OBJ = $(SRC:.c=.o)
OBJ = $(patsubst $(SRC_DIR)/%.c,$(BIN_DIR)/%.o,$(SRC))
Now you'll find that your object rule,
.c.o:
...
doesn't work, because it expects to find the source file in the same place where the object file should go (i.e. $(OBJ_DIR)). So replace this rule with:
$(BIN_DIR)/%.o: $(SRC_DIR)/%.c
$(CC) $(INCLUDES) -c $< -o $#
I notice that you have no provision for building $(BIN_DIR)/t.o and $(BIN_DIR)/test.o, but the app needs them. You should look into that.
Further refinements are possible, but this is a start.
Your SRC has a relative path, and your OBJ is just the SRC with the extension changed to. o
So OBJ will contain this:
../src/add.o
../src/sub.o
And there is where the .o will be created.
Make these changes and it will work:
SRC = add.c \
sub.c
.c.o:
$(CC) $(INCLUDES) -c ../src/$< -o ../bin/$#

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