Get make to recompile only unchanged source files - makefile

Question

I'm trying to get my Makefile to compile only changed source files. In the Makefile below, I would like the targets: %.o : ${SOURCE_DIR}/%.c and %.o : ${SOURCE_DIR}/%.s to only compile if the source file has changed, or the corresponding .o object file does not exist.
Not entirely sure what's wrong here, can someone please offer some advice?
# Project name
# ---------------------------------------------------------------------------------------------------------------------
PROJECT_NAME = stm32f4_template
# Source configuration
# ---------------------------------------------------------------------------------------------------------------------
OUT_DIR = ./Build
SOURCE_DIR = ./Src
SOURCES = main.c
SOURCES += startup.s
C_SOURCES = $(filter %.c, $(SOURCES))
ASM_SOURCES += $(filter %.s, $(SOURCES))
OBJECTS = $(C_SOURCES:.c=.o)
OBJECTS += $(ASM_SOURCES:.s=.o)
# Tools
# ---------------------------------------------------------------------------------------------------------------------
CC = arm-none-eabi-gcc
LD = arm-none-eabi-ld -v
CP = arm-none-eabi-objcopy
OD = arm-none-eabi-objdump
# Compilation, linker and other tool flags
# ---------------------------------------------------------------------------------------------------------------------
CFLAGS = -I./ -c -fno-common -O0 -g -mcpu=cortex-m4 -mthumb
LFLAGS = -nostartfiles -TLinker/memory.ld -TLinker/sections.ld
CPFLAGS = -Obinary
ODFLAGS = -S
# Target: all ---------------------------------------------------------------------------------------------------------
#
all: setup $(PROJECT_NAME).elf
#echo "Done! $?"
# Target: setup -------------------------------------------------------------------------------------------------------
#
setup:
#mkdir -p $(OUT_DIR)
# Target: $(PROJECT_NAME).elf
# ---------------------------------------------------------------------------------------------------------------------
$(PROJECT_NAME).elf: $(OBJECTS)
#echo "Linking $#"
$(LD) $(LFLAGS) -o ${OUT_DIR}/main.elf $(OUT_DIR)/main.o
#echo
# Target %.o (.c sources)
# ---------------------------------------------------------------------------------------------------------------------
%.o : ${SOURCE_DIR}/%.c # --> Execute only if source changed!!!
#echo "Compiling $<"
$(CC) $(CFLAGS) $< -o $(OUT_DIR)/$#
#echo
# Target %.o (.s sources)
# ---------------------------------------------------------------------------------------------------------------------
%.o : ${SOURCE_DIR}/%.s # --> Execute only if source changed!!!
#echo "Compiling $<"
$(CC) $(CFLAGS) $< -o $(OUT_DIR)/$#
#echo
# Target: clean
# ---------------------------------------------------------------------------------------------------------------------
clean:
#echo "Cleaning build output..."
#rm -rf $(OUT_DIR)

Answer 1

This rule:
%.o : ${SOURCE_DIR}/%.c # --> Execute only if source changed!!!
#echo "Compiling $<"
$(CC) $(CFLAGS) $< -o $(OUT_DIR)/$#
The problem is that the target of this rule is main.o, so Make uses it in an attempt to build main.o, because another target demands main.o, but what this rule actually builds is Build/main.o. Make keeps running this rule because it sees that main.o isn't there (and the rule for the elf file uses Build/main.o, which Make keeps rebuilding unawares).
I suggest you change it:
OBJECTS = $(patsubst %.c, $(OUT_DIR)/%.o, $(C_SOURCES))
$(OUT_DIR)/%.o : ${SOURCE_DIR}/%.c # --> this should work
#echo "Compiling $<"
$(CC) $(CFLAGS) $< -o $#
The same goes for the other %.o rule.