VHDL 2008 Width mismatch - vhdl

Question

I am facing a width mismatch issue when I am using a 3-dimensional array using VHDL.
Error is :
[Synth 8-549] port width mismatch for port 'KERNEL_OUT[0]': port width = 16, actual width = 32 ["C:/project_2/src/top.vhd":29]
As we can see that line #30 is actually 32 bits and the component is having an unconstrained port. So instead of taking the length from the connected port, it using the value from previously instantiated component.
I've made a very minimal design out of it. I'm using Vivado 2018.2 There are high chances that this might be a tool issue. But it will be very much helpful if someone can tell me if I'm doing something wrong.
top.vhd
library ieee;
use ieee.std_logic_1164.all;
use work.style_pack.all;
-------------------------------------------------------------------------------
-- Entity
-------------------------------------------------------------------------------
entity top is
port(
dummy : in std_logic
);
end entity top;
architecture arch_top of top is
signal KernelInt1 : StdVectorArrayTp(0 to 4)(15 downto 0);
signal KernelInt2 : StdVectorArrayTp(0 to 4)(31 downto 0);
begin
--
INST_pixel_to_matrix_1 : entity work.pixel_to_matrix
port map (
KERNEL_OUT => KernelInt1
);
--
INST_pixel_to_matrix_2 : entity work.pixel_to_matrix
port map (
KERNEL_OUT => KernelInt2
);
end architecture arch_top;
pixel_to_matrix.vhd
library ieee;
use ieee.std_logic_1164.all;
-----------------------
-- ENTITY DEFINITION --
-----------------------
entity pixel_to_matrix is
port (
KERNEL_OUT : out StdVectorArrayTp
);
end pixel_to_matrix;
architecture arch_pixel_to_matrix of pixel_to_matrix is
begin
end architecture arch_pixel_to_matrix;
style_pack.vhd
library IEEE;
use IEEE.std_logic_1164.all;
package style_pack is
type StdVectorArrayTp is array (integer range <>) of std_logic_vector;
end style_pack;
package body style_pack is
end style_pack;
I've posted same question at https://forums.xilinx.com/t5/Synthesis/VHDL-2008-width-mismatch-on-multiple-instantiations/td-p/1164467
where I uploaded the code with Vivado project https://forums.xilinx.com/xlnx/attachments/xlnx/SYNTHBD/36597/2/project_1.zip
Edit :
Project with 3D array StdVectorArrayTp https://forums.xilinx.com/xlnx/attachments/xlnx/SYNTHBD/36602/1/project_2.zip