"Indexed name is not a std_logic_vector" - vhdl

Question

I am trying to use "port map" in my code, but I don't know how to fix an error. It says "indexed name is not a std_logic_vector" for both port map. I have to implement the circuit below.
I did the counter and the MPG and added them as components, they work separately. I will leave the code for the circuit. It says that it is a problem at "port map".
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test_env is
Port ( clk : in STD_LOGIC;
btn : in STD_LOGIC_VECTOR (15 downto 0);
sw : in STD_LOGIC_VECTOR (15 downto 0);
led : out STD_LOGIC_VECTOR (15 downto 0));
end test_env;
architecture Behavioral of test_env is
component MPG
Port(clk : in STD_LOGIC;
btn : in STD_LOGIC_VECTOR (15 downto 0);
enable : out STD_LOGIC);
end component;
component counter
Port ( clk : in STD_LOGIC;
btn : in STD_LOGIC_VECTOR (15 downto 0);
sw : in STD_LOGIC_VECTOR (15 downto 0);
led: out STD_LOGIC_VECTOR (15 downto 0));
end component;
signal en: STD_LOGIC;
signal s: STD_LOGIC_VECTOR(2 downto 0);
signal dcd: STD_LOGIC_VECTOR (7 downto 0);
begin
--led<=sw;
--an<=btn(3 downto 0);
--cat<=(others=>'0');
process(s)
begin
case s is
when "000" => dcd<="00000001";
when "001" => dcd<="00000010";
when "010" => dcd<="00000100";
when "011" => dcd<="00001000";
when "100" => dcd<="00010000";
when "101" => dcd<="00100000";
when "110" => dcd<="01000000";
when others => dcd<="10000000";
end case;
end process;
monopulse: MPG port map(clk, btn, en);
count: counter port map(clk, btn, sw(0), s);
led(7 downto 0)<= dcd;
end Behavioral;
I will leave the codes for the components too
Counter(16 bits)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( clk : in STD_LOGIC;
btn : in STD_LOGIC_VECTOR (15 downto 0);
sw : in STD_LOGIC_VECTOR (15 downto 0);
led: out STD_LOGIC_VECTOR (15 downto 0));
end counter;
architecture Behavioral of counter is
signal Q: STD_LOGIC_VECTOR (15 downto 0);
begin
process(btn)
begin
if rising_edge(clk) then
if(btn(0)='1') then
if(sw(0)='1') then
Q<= Q + "0000000000000001";
else Q<=Q - "0000000000000001";
end if;
end if;
end if;
end process;
led<=Q;
end Behavioral;
MPG
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MPG is
Port(clk : in STD_LOGIC;
btn : in STD_LOGIC_VECTOR (15 downto 0);
enable : out STD_LOGIC);
end MPG;
architecture Behavioral of MPG is
signal count : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal Q1 : STD_LOGIC;
signal Q2 : STD_LOGIC;
signal Q3 : STD_LOGIC;
begin
enable<=Q2 and (not(Q3));
process(btn)
begin
if rising_edge(clk) then
count<=count + "0000000000000001";
end if;
end process;
process(btn)
begin
if rising_edge(clk) then
if count(15 downto 0)= "1111111111111111" then
Q1<=btn(1);
end if;
end if;
end process;
process(btn)
begin
if rising_edge(clk) then
Q2<=Q1;
Q3<=Q2;
end if;
end process;
end Behavioral;
If anyone can help me, thank you very much!!