How to transfer data from one process to another? - vhdl

As an example, in the first process I have a binary number that I want to transfer to a second process. How to I do this?
Do i need to use something called a FIFO?
If I need to use a FIFO must I use it? Are there any alternatives?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pwm_control_1 is
port (
--inputs and outputs for clock divider-------------------------------------------------------
clk_in : in std_logic ;
clr : in std_logic;
pwm_testing: out bit;
pwm_out: out bit;
key_0:in bit;
green_led:out bit
);
end pwm_control_1;
architecture Behavioral of pwm_control_1 is
signal compare:std_logic_vector( 8 downto 0);
signal q:std_logic_vector (8 downto 0);-- q is for the clock divider ,q can get till 23
signal q_1:std_logic_vector (23 downto 0);
signal pwm_testing_signal : bit;
signal test : std_logic_vector(8 downto 0);
signal step_10_dc : std_logic_vector(8 downto 0);
signal step_5_dc : std_logic_vector(8 downto 0);
signal duty_cycle_0 : std_logic_vector(8 downto 0);
signal duty_cycle_counter : std_logic_vector(8 downto 0);
signal duty_cycle_counter_refresh : std_logic_vector(8 downto 0);
begin
test <= "000000000";
step_10_dc <= "000110011";
step_5_dc <= "000011010";
duty_cycle_counter <= "000000000";
duty_cycle_counter_refresh <= "000000000";
--
key_testing :process (key_0)
begin
if (key_0='0') then
green_led <='1';
duty_cycle_counter <= (duty_cycle_counter+step_5_dc);-- counter for adding the limit of the PWM
else
green_led <='0';
end if;
end process key_testing;
` duty_cycle_counter_refresh <=duty_cycle_counter;
add_5_or_10_duty_cycle :process(clk_in,clr,q ,key_0)
begin
if (clk_in'event and clk_in='1') then -- starting the q counter
q<= q+1; --first I torn on the counter q that is used for clock driver then
if (q<=(duty_cycle_counter_refresh )) then pwm_testing_signal <='1';
else
pwm_testing_signal <='0';
end if ;
end if;
end process add_5_or_10_duty_cycle;
pwm_testing <=pwm_testing_signal;
end Behavioral;

Related

"Indexed name is not a std_logic_vector"

I am trying to use "port map" in my code, but I don't know how to fix an error. It says "indexed name is not a std_logic_vector" for both port map. I have to implement the circuit below.
I did the counter and the MPG and added them as components, they work separately. I will leave the code for the circuit. It says that it is a problem at "port map".
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test_env is
Port ( clk : in STD_LOGIC;
btn : in STD_LOGIC_VECTOR (15 downto 0);
sw : in STD_LOGIC_VECTOR (15 downto 0);
led : out STD_LOGIC_VECTOR (15 downto 0));
end test_env;
architecture Behavioral of test_env is
component MPG
Port(clk : in STD_LOGIC;
btn : in STD_LOGIC_VECTOR (15 downto 0);
enable : out STD_LOGIC);
end component;
component counter
Port ( clk : in STD_LOGIC;
btn : in STD_LOGIC_VECTOR (15 downto 0);
sw : in STD_LOGIC_VECTOR (15 downto 0);
led: out STD_LOGIC_VECTOR (15 downto 0));
end component;
signal en: STD_LOGIC;
signal s: STD_LOGIC_VECTOR(2 downto 0);
signal dcd: STD_LOGIC_VECTOR (7 downto 0);
begin
--led<=sw;
--an<=btn(3 downto 0);
--cat<=(others=>'0');
process(s)
begin
case s is
when "000" => dcd<="00000001";
when "001" => dcd<="00000010";
when "010" => dcd<="00000100";
when "011" => dcd<="00001000";
when "100" => dcd<="00010000";
when "101" => dcd<="00100000";
when "110" => dcd<="01000000";
when others => dcd<="10000000";
end case;
end process;
monopulse: MPG port map(clk, btn, en);
count: counter port map(clk, btn, sw(0), s);
led(7 downto 0)<= dcd;
end Behavioral;
I will leave the codes for the components too
Counter(16 bits)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( clk : in STD_LOGIC;
btn : in STD_LOGIC_VECTOR (15 downto 0);
sw : in STD_LOGIC_VECTOR (15 downto 0);
led: out STD_LOGIC_VECTOR (15 downto 0));
end counter;
architecture Behavioral of counter is
signal Q: STD_LOGIC_VECTOR (15 downto 0);
begin
process(btn)
begin
if rising_edge(clk) then
if(btn(0)='1') then
if(sw(0)='1') then
Q<= Q + "0000000000000001";
else Q<=Q - "0000000000000001";
end if;
end if;
end if;
end process;
led<=Q;
end Behavioral;
MPG
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MPG is
Port(clk : in STD_LOGIC;
btn : in STD_LOGIC_VECTOR (15 downto 0);
enable : out STD_LOGIC);
end MPG;
architecture Behavioral of MPG is
signal count : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal Q1 : STD_LOGIC;
signal Q2 : STD_LOGIC;
signal Q3 : STD_LOGIC;
begin
enable<=Q2 and (not(Q3));
process(btn)
begin
if rising_edge(clk) then
count<=count + "0000000000000001";
end if;
end process;
process(btn)
begin
if rising_edge(clk) then
if count(15 downto 0)= "1111111111111111" then
Q1<=btn(1);
end if;
end if;
end process;
process(btn)
begin
if rising_edge(clk) then
Q2<=Q1;
Q3<=Q2;
end if;
end process;
end Behavioral;
If anyone can help me, thank you very much!!

VHDL-can't add numbers?

Hello I want to build a clock on my ALTERA DE2 that I can adjust the length of by pressing keys.
Now the problem is that when I convert from STD_LOGIC_VECTOR to UNSIGNED the code does not work:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_unsigned.all; Do not use with numeric_std
entity Adjust_Clock_4_buttens is
port(
clk,clk1 : in STD_LOGIC;
minutes_plus, minutes_minus,houres_plus,houres_minus : in STD_LOGIC;
minutes : IN STD_LOGIC_VECTOR(5 downto 0);
houres : IN STD_LOGIC_VECTOR(4 downto 0);
output_minutes : out STD_LOGIC_VECTOR(5 downto 0);
output_houres : out STD_LOGIC_VECTOR(4 downto 0);
LED_0 : OUT STD_LOGIC;
LED_1 : OUT STD_LOGIC;
LED_2 : OUT STD_LOGIC;
LED_3 : OUT STD_LOGIC
);
end entity Adjust_Clock_4_buttens ;
architecture behavioral of Adjust_Clock_4_buttens is
signal button1_r : std_logic_vector(2 downto 0);
signal button2_r : std_logic_vector(2 downto 0);
signal button3_r : std_logic_vector(2 downto 0);
signal button4_r : std_logic_vector(2 downto 0);
-- signal minutes_total : unsigned(5 downto 0) := (others => '0');
-- signal houres_total : unsigned(4 downto 0) := (others => '0');
signal minutes_total : unsigned(5 downto 0);
signal houres_total : unsigned(4 downto 0);
begin
process(clk)
begin
if (rising_edge(clk) )then
minutes_total<=unsigned(minutes);
houres_total<=unsigned(houres);
-- Shift the value of button in button_r
-- The LSB is unused and is there solely for metastability
button1_r <= button1_r(button1_r'left-1 downto 0) & minutes_plus;
button2_r <= button2_r(button2_r'left-1 downto 0) & minutes_minus;
button3_r <= button3_r(button3_r'left-1 downto 0) & houres_plus;
button4_r <= button4_r(button4_r'left-1 downto 0) & houres_minus;
if button1_r(button1_r'left downto button1_r'left-1) = "01" then -- Button1 rising --button1_r[2:1]
minutes_total <= (minutes_total + 1);
LED_0<='1';LED_1<='0';LED_2<='0';LED_3<='0';
elsif button2_r(button2_r'left downto button2_r'left-1) = "01" then -- Button2 rising --button1_r[2:1]
minutes_total <= (minutes_total-1 );
LED_0<='0';LED_1<='1';LED_2<='0';LED_3<='0';
end if;
if button3_r(button3_r'left downto button3_r'left-1) = "01" then -- Button1 rising --button1_r[2:1]
houres_total <= (houres_total + 1);
LED_0<='0';LED_1<='0';LED_2<='1';LED_3<='0';
elsif button4_r(button4_r'left downto button4_r'left-1) = "01" then -- Button2 rising --button1_r[2:1]
houres_total<= (houres_total-1 );
LED_0<='0';LED_1<='0';LED_2<='0';LED_3<='1';
end if;
end if;
end process;
output_minutes <= std_logic_vector(minutes_total);
output_houres <= std_logic_vector(houres_total);
end architecture behavioral ;
So in this code I get the time from another block the problem start when I try to add minutes and hours and for some reason it does not react to pressing of the keys. Could anyone explain maybe why is that?
The problem might be that you only have the clock in the sensitivity list of your process. Try adding the buttons in the sensitivity list, since they drive your if conditions. (Not sure if that's the problem but I guess it's worth a try)
minutes_total<=unsigned(minutes);
is on 2 lines, inside and outside of the process, which generates multiple line drivers, and will not work, ever!
(didn't read the rest of the code, there may be other problems, like hours not taking an e)
Now that it's inside the process, you need to rename minutes_total as minute_source, else you're incrementing the value only for the one clock cycle when you have a button edge!

Can't resolve multiple constant drivers for net

I wrote this code. I want to count the numbers that I pressed they key_0 and if I press 2 times then the red led will turn on, how ever I get this error:
Can't resolve multiple constant drivers for net.
The thing is that I try to torn on 2 process at the same time how ever this tow process have the same variable: duty_cycle_counter.
What is the problem?
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity Pwm_control is
generic(display_resolution : INTEGER := 8);
port(
key_0 : in BIT;
green_led : out BIT;
red_led : out BIT
);
end Pwm_control;
architecture Behavioral of Pwm_control is
signal counter : std_logic_vector(display_resolution downto 0);
signal general_counter : std_logic_vector(23 downto 0); -- general_counter is for the clock divider , can get till 23
signal step_10_dc : STD_LOGIC_VECTOR(8 downto 0); --10 step PWM
signal step_5_dc : STD_LOGIC_VECTOR(8 downto 0); --5 step PWM
signal starting_value_0 : STD_LOGIC_VECTOR(8 downto 0); --0 step PWM
signal duty_cycle_counter : STD_LOGIC_VECTOR(8 downto 0);
begin
starting_value_0 <= "000000000";
step_5_dc <= "000011010";
step_10_dc <= "000110011";
duty_cycle_counter <= "000000000";
key_testing : process(key_0) --
begin
if (key_0 = '0') then
green_led <= '1';
duty_cycle_counter <= (duty_cycle_counter + step_5_dc);
else
green_led <= '0';
end if;
end process key_testing;
key_test_red_led : process(duty_cycle_counter)
begin
if (step_10_dc <= duty_cycle_counter) then
red_led <= '1';
end if;
end process key_test_red_led;
end Behavioral;
You're driving duty_cycle_counter continuously with 0 and trying to update it in the key_testing process. It looks like you wanted a start value (possible in most RAM-based FPGAs) or a reset, though in real life it will have some value so you could just leave out the initialization.

VHDL - Index out range even If I made concurrent checking using when-else

I'm implementing a register file where I wanna read asynchronously and write on the rising edge.
I made concurrent checks on the addresses and the writing occurs inside a process.
However, it always cause me a fatal error and I don't know why!
Here's my code if anyone could help and tell me how can I read asynchronously and write on rising edge
Thank you!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RegFile is
port(
outData1 : out std_logic_vector(15 downto 0);
outData2 : out std_logic_vector(15 downto 0);
inData : in std_logic_vector(15 downto 0);
writeEn : in std_logic;
reg1Sel : in std_logic_vector(2 downto 0);
reg2Sel : in std_logic_vector(2 downto 0);
writeRegSel : in std_logic_vector(2 downto 0);
clk : in std_logic
);
end RegFile;
architecture Register_File of RegFile is
type registerFile is array(0 to 5) of std_logic_vector(15 downto 0);
signal registers : registerFile;
signal reg1Address,reg2Address : integer;
signal reg1FinalAddressing,reg2FinalAddressing : std_logic_vector(2 downto 0);
begin
--Conversion of logic vector to unsigned integer
reg1Address <= to_integer(unsigned(reg1Sel));
reg2Address <= to_integer(unsigned(reg2Sel));
reg1FinalAddressing <= reg1Sel when (reg1Address<6 ) else
(others => '0');
reg2FinalAddressing <= reg2Sel when (reg2Address<6 ) else
(others => '0');
outData1 <= registers(to_integer(unsigned(reg1FinalAddressing)));
outData2 <= registers(to_integer(unsigned(reg2FinalAddressing)));
process (clk) is
begin
-- Reading from Registers 1 and 2
if rising_edge(clk) then
-- Writing to Register file Case Enabled
if writeEn = '1' then
registers(to_integer(unsigned(writeRegSel))) <= inData;
-- Case a value being written to register file, it will be out simultaneously if
-- the register was already selected. (The updated values are being released instantly).
if reg1Sel = writeRegSel then
outData1 <= inData;
end if;
if reg2Sel = writeRegSel then
outData2 <= inData;
end if;
end if;
end if;
end process;
end Register_File;

Communication PC-DE0 Nano using UART

I'm trying to connect my FPGA with my laptop using the serial protocol. For that purpose, I implemented the UART protocol on the FPGA side.
The connection between the FPGA and the Laptop is done with the UART-TTL to USB converter. I Get the wrong frame on the Laptop side.
Thus, I analyse my frame continuously using a logic analyzer, I observed that the frame sent wasn't stable, i.e sometimes a wrong frame is received instead of the one sent.
Below is the code for the serial core :
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TX is
port(
CLK: in std_logic;
START: in std_logic;
BUSY : out std_logic;
DATA: in std_logic_vector(7 downto 0);
TX_LINE: out std_logic
);
end TX;
architecture MAIN of TX is
signal PRSCL : integer range 0 to 5208:=0;
signal index : integer range 0 to 9:=0;
signal DATAFLL : std_logic_vector (9 downto 0);
signal TX_FLAG: STD_LOGIC:='0';
begin
process(CLK)
begin
if(CLK'EVENT and CLK='1') then
if(TX_FLAG='0' and START='1') then
TX_FLAG<='1';
BUSY<='1';
DATAFLL(0)<='0';
DATAFLL(9)<='1';
DATAFLL(8 downto 1)<=DATA;
TX_LINE<='1';
end if;
-- send data , 50MHz /9600=5208 (9600: the baudrate)
IF(TX_FLAG='1') then
IF (PRSCL <5207) then
PRSCL<=PRSCL+1;
else
PRSCL<=0;
end if;
IF(PRSCL=2600)THEN
TX_LINE<=DATAFLL(INDEX);
IF(INDEX<9)THEN
INDEX<=INDEX+1;
ELSE
TX_FLAG<='0';
BUSY<='0';
INDEX<=0;
END IF;
END IF;
END IF;
END IF;
end process ;
end MAIN;
The control unit to instantiate the serial core is below :
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity UART is
port (
CLOCK_50: in std_logic;
SW: in std_logic_vector(3 downto 0);
KEY: in std_logic_vector(1 downto 0);
LEDG : out std_logic_vector (7 downto 0);
UART_TXD : out std_logic;
UART_RXD: in std_logic
);
end UART ;
ARCHITECTURE MAIN OF UART IS
SIGNAL TX_DATA: STD_LOGIC_VECTOR(7 downto 0);
SIGNAL TX_START: STD_LOGIC:='0';
SIGNAL TX_BUSY: STD_LOGIC:='0';
SIGNAL RX_DATA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL RX_BUSY: STD_LOGIC:='0';
COMPONENT TX
PORT(
CLK:IN STD_LOGIC;
START:IN STD_LOGIC;
BUSY:OUT STD_LOGIC;
DATA: IN STD_LOGIC_VECTOR(7 downto 0);
TX_LINE:OUT STD_LOGIC
);
END COMPONENT TX;
BEGIN
C1: TX PORT MAP (CLOCK_50,TX_START,TX_BUSY,TX_DATA,UART_TXD);
--C2: RX PORT MAP (CLOCK_50,UART_RXD,RX_DATA,RX_BUSY);
PROCESS(CLOCK_50)
BEGIN
IF(CLOCK_50'EVENT AND CLOCK_50='1')THEN
IF(KEY(0)='1' AND TX_BUSY='0')THEN -- Key(0)='0' MEAN that the key is pressed
TX_DATA<="0000" & SW(3 DOWNTO 0);
TX_START<='1';
LEDG<=TX_DATA;
ELSE
TX_START<='0';
TX_DATA<=(others=>'0') ;
END IF;
END IF;
END PROCESS;
END MAIN;
Thanks for you help.
Best regards,
Any asynchronous input have to be resynchronized before use, otherwise your circuit will become metastable and erratic behaviour will follow. On your top level, sw and key are asynchronous.
A synchronization circuit is typically 2 cascaded flip-flops, only the output of the second flip-flop should be used in your code:
...
signal sw_resync1 : std_logic_vector(3 downto 0);
signal sw_resync2 : std_logic_vector(3 downto 0);
signal key_resync1 : std_logic_vector(3 downto 0);
signal key_resync2 : std_logic_vector(3 downto 0);
begin
RESYNC: process(CLOCK_50)
begin
if (CLOCK_50'event and CLOCK_50 = '1') then
SW_resync1 <= SW;
SW_resync2 <= SW_resync1;
KEY_resync1 <= KEY;
KEY_resync2 <= KEY_resync1;
end if;
end process RESYNC;
...
IF(KEY_resync2(0)='1' AND TX_BUSY='0')THEN -- Key(0)='0' MEAN that the key is pressed
TX_DATA<="0000" & SW_resync2(3 DOWNTO 0);
...
You should also be aware that mechanical inputs (suck as sw and key) should be debounced or you will read several transitions for the same key stroke.

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