I'm a total noob in ISE Design Suite 14.7 and I don't know a thing.
I'm trying to make a SR latch (I know there is a SR latch in ISE but I want to create it myself to practice).
the SR latch itself works fine but I get an error from Top_Module.
here is the code for SR latch:
and the top module code and the error when I want to implement it:
It works fine when I change the top module to SRlatch.v and not the topmodule.v.
what should I do?
please don't say I have to search on google because I don't understand a thing.
I solved the problem. What I wrote was rudimentary and also wasn't well connected and it couldn't implement it.
But I wanted to see the result by using ModelSim and it was fine with it and compiled it.
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I am currently setting up a Cocotb based verification environment.
I just discovered that the example provided with Cocotb don't work in my case if using VHDL, because my simulator has no FLI (foreign language interface).
I get the following message:
Error (suppressible): (vsim-FLI-3155) The FLI is not enabled in this version of ModelSim.
(I have the Altera Starter version of ModelSim, and indeed FLI is not included).
What surprises me is that the example works with Verilog. From my understanding, Verilog is not using FLI, but VPI.
Can someone explain me a little bit if the need for FLI is mandatory, and what feature can enable it in Cocotb?
Another question: What if my top is in Verilog, but the rest of my design in VHDL? Should it work?
Cocotb has an internal abstraction layer (GPI) for FLI, VPI and VHPI. E.g. if you use Cocotb with GHDL, it's using just VPI. You can try to compile Cocotb against VPI instead of FLI and load the VPI library instead of the FLI library.
I have a vhdl design that is created in Xilinx ISE and I would like to bring it over to the XPS/EDK 14.2 as a pcore. The issue is, I am not really sure how I should be hooking it up. The XPS utility gives me the option of an AXI Burst bus. Am I suppose to create an interface to hook up the AXI signals to my module? I am not really sure how I am suppose to use it as a pcore, since I am new to the XPS tool. I was under the impression the XPS tool would make the appropriate hook ups for me (i.e. ACLK would connect to my clock, etc.).
Any background information would be appreciated. I am only finding tutorials with the older version of XPS and it doesn't really cover my issue.
Have you looked into tools like ImpulseC from Impulse Accelerated Technologies?
I have had years of good results using that tool to develop pcores in ANSI-C and them exporting the results into correctly formed Xilinx pcores.
If you asked, I'm sure you could get a demo license to see if it would help in your situation.
It spits everything out in VHDL and you can read through the results to see how to do it.
I am using the excellent open-source FPGALink utility to program a FPGA, through USB and JTAG.
Classically, I generate a .bit file correctly, using a set of scripts gluing the various stages of the Xilinx synthesis process.
That works like a charm : just after the bitstream has been loaded into FPGA, I can play with my embedded design on a Nexys2 FPGA board (from Digilent).
However, now I am facing a new challenge : I'd like to flash my .bit file into the PROM. It seems I need to generate a .mcs file now. I found a tutorial but it focuses on Xilinx GUI, that I really want to avoid.
How can I manage to do this, only based on scripts ? (update : this link seems to give a detailed procedure)
And then how to load this in PROM, using FPGALink ?
It seems that everything is explained here.
I'm using VHDL on Xilinx ISE to generate a schematic of the register transfer logic in my project. I know ISE does a number of optimizations and gate reductions before spitting out the RTL and Technology schematics. What I want to do is to export the netlist of these schematics into some file so I can use that for my own program. Is there any way to do this? I keep reading about ngc files, but the contents of the ngc file generated upon synthesis make absolutely no sense.
Please let me know if you've done this before, I'd love to see how this is done. If it's not doable on ISE, can you recommend a tool that could do it?
EDIF is an industry standard format for describing netlists - there are numerous tools for interpreting them and you could easily roll your own since it's a documented textual format.
You can convert an .ngc into an edif file by running the Xilinx tool ngc2edif included in the ISE suite.
Is there any quite good tool to generate State Machine graph from VHDL code? I'm using Xilinx ISE Webpack. Cheers!
Active HDL has a feature called "Code2Graphics" which supports this.
Additionally, some synthesis tools (typically ones you would have to pay for) also support this.
Note that an RTL view is more commonly available in synthesis tools (such as XST).
Modelsim SE (and DE?) have these kind of things. But, not for free :-(