I am currently setting up a Cocotb based verification environment.
I just discovered that the example provided with Cocotb don't work in my case if using VHDL, because my simulator has no FLI (foreign language interface).
I get the following message:
Error (suppressible): (vsim-FLI-3155) The FLI is not enabled in this version of ModelSim.
(I have the Altera Starter version of ModelSim, and indeed FLI is not included).
What surprises me is that the example works with Verilog. From my understanding, Verilog is not using FLI, but VPI.
Can someone explain me a little bit if the need for FLI is mandatory, and what feature can enable it in Cocotb?
Another question: What if my top is in Verilog, but the rest of my design in VHDL? Should it work?
Cocotb has an internal abstraction layer (GPI) for FLI, VPI and VHPI. E.g. if you use Cocotb with GHDL, it's using just VPI. You can try to compile Cocotb against VPI instead of FLI and load the VPI library instead of the FLI library.
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I'm a total noob in ISE Design Suite 14.7 and I don't know a thing.
I'm trying to make a SR latch (I know there is a SR latch in ISE but I want to create it myself to practice).
the SR latch itself works fine but I get an error from Top_Module.
here is the code for SR latch:
and the top module code and the error when I want to implement it:
It works fine when I change the top module to SRlatch.v and not the topmodule.v.
what should I do?
please don't say I have to search on google because I don't understand a thing.
I solved the problem. What I wrote was rudimentary and also wasn't well connected and it couldn't implement it.
But I wanted to see the result by using ModelSim and it was fine with it and compiled it.
I would like to launch an unit delay RTL simulation using Questasim 10.1. I've looked how to compile the design and I see there is an option +delay_mode_unit for compiling verilog files. My design is vhdl.
Is there an option for this kind of design?
By refering to Modelsim 10.1c User Manual- Chapter 7, Cell Libraries, you can find how Modelsim can support various Verilog ASIC and FPGA cell libraries. Unit Delay Mode is explained one page after in the manual.
Concerning VHDL, I can't find a similar section where Modelsim has a confirmed support. However, in Chapter 14, VHDL VITAL SDF, you can find how to enable timing for VITAL cells only. You can read the following section SDF to VHDL Generic Matching for more help.
Also have a look at Chapter 6, VITAL Usage and Compliance on how to make a working setup for VHDL.
I am trying to make simple version of the Y86 CPU. I would like a reference Y86 verilog code.
Is this available?
The Y86 Instruction Set Architecture is a pseudo-language based on x86 for teaching purposes.
I am not sure that the verilog code for it exists under an open-source licence and as part of a course I would have thought it was coursework to write it yourself.
I have xilinx macros for uart (.edn files) and i don't know how to use the in activehdl
when i simulate the macros the give uninitialized output ? so what if any one can help me with the right way to use the macro ...?
Use the Xilinx uniMacro library. You may need to compile or download it for your simulator.
ActiveHDL is a simulator package. It typically operates by compile VHDL or Verilog code. The "macros" you are refering to with the extension ".edn" are EDIF netlist files. These are not files that can typically be used by simulator, but are in almost all cases only usable by the synthesizer for the exact device they are targeting.
It may be the case that ActelHDL can import EDIF files. In this case, it still will only work if the primitives used by the EDIF file are also added as part of the project. As another answer said, this most likely would be primitives from the Xilinx unisim library.
The best option is to probably run the EDIF files you have through the Xilinx tools (specifically "Translate" (ngdbuild) and "Generate Simulation Netlist" (netgen)) to generate a simulation model for these pieces. The result will likely require the Xilinx unisim and simprims libraries, which are usually available precompiled for most simulators, but can also easily just be pointed to the source in the Xilinx ISE install.
Is there any quite good tool to generate State Machine graph from VHDL code? I'm using Xilinx ISE Webpack. Cheers!
Active HDL has a feature called "Code2Graphics" which supports this.
Additionally, some synthesis tools (typically ones you would have to pay for) also support this.
Note that an RTL view is more commonly available in synthesis tools (such as XST).
Modelsim SE (and DE?) have these kind of things. But, not for free :-(