Im new to VHDL and I'm doing some university exercises. It was all great until today when I got an error that I don't understand the reason of why it appears. Hope you could help me. (Software: Quartus Prime)
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity AddSub4 is
port(a, b : in std_logic_vector(3 downto 0);
sub : in std_logic;
s : out std_logic_vector(3 downto 0);
cout : out std_logic);
end AddSub4;
architecture Structural of AddSub4 is
signal s_b : std_logic_vector (3 downto 0);
begin
sub_mux: s_b <= b when (sub='0') else
not b;
final: entity work.Adder4(Structural)
port map(cin => sub,
a => a,
b => b,
cout => cout,
s => s);
end Structural;
architecture Behave of AddSub4 is
signal val1, val2, valFinal : unsigned(4 downto 0);
begin
val1 <= '0' & unsigned(a);
val2 <= '0' & unsigned(b);
valFinal <= (val1 + val2) when (sub = '0') else (val1 - val2);
s <= std_logic_vector(valFinal(3 downto 0));
cout <= std_logic(valFinal(4));
end Behave;
The error in the terminal:
Error (10482): VHDL error at AddSub4.vhd(30): object "unsigned" is used but not declared
you need to add a library you can either
use ieee.numeric_std.all ;
use ieee.std_logic_unsigned.all;
Related
The entity was created by the IDE and seemingly randomly started giving me a syntax error. I tried restarting IDE since that works sometimes, didn't work this time.
The compiler says Syntax error near "end". The problem line is end design1;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity design1 is
Port ( Reg_A : in STD_LOGIC_VECTOR(31 downto 0);
Reg_B : in STD_LOGIC_VECTOR(31 downto 0);
Op_Sel : in STD_LOGIC_VECTOR(3 downto 0);
C_In : in STD_LOGIC;
C_Out : out STD_LOGIC;
ALU_Out : out STD_LOGIC_VECTOR(31 downto 0);
end design1;
architecture Behavioral of design1 is
begin
process is
begin
if(Op_Sel(3) = '0') then
if(Op_Sel(2) = '0') then --performing arithmetic
if(Op_Sel(1 downto 0) = "00") then --transfer A
elsif(Op_Sel(1 downto 0) = "01") then --increment A
elsif(Op_Sel(1 downto 0) = "10") then --decrement A
elsif(Op_Sel(1 downto 0) = "11") then --add
end if;
end if;
elsif(Op_Sel(2) = '1') then --performing logic operations
if(Op_Sel(1 downto 0) = "00") then --Not A
if(Op_Sel(1 downto 0) = "01") then --A and B
if(Op_Sel(1 downto 0) = "10") then --A or B
if(Op_Sel(1 downto 0) = "11") then --A xor B
elsif(Op_Sel(3) = '1') then --Shifting
if(Op_Sel(2) = '0') then --right shift
elsif(Op_Sel(2) = '1' then --left shift
end if;
end if;
end process;
end Behavioral;
Heyo!
I've been trying to get into programming vhdl again for some upcoming classes and tried to do an simple 8-bit adder and wanted to test it with a testbench. (I'm working with the Vivado Xilinx Software btw~)
I don't get any syntax errors, but it shows the variables as "U" (I guess undefined?)
Hope it's easy to see what I did (and why lol). Yea but I can't really find the problem??
My code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity addierer is
Port ( a : in STD_LOGIC_VECTOR(7 downto 0);
b : in STD_LOGIC_VECTOR(7 downto 0);
cin : in STD_LOGIC;
s : out STD_LOGIC_VECTOR(7 downto 0);
cout : out STD_LOGIC);
end addierer;
architecture Behavioral of addierer is
COMPONENT volladdierer is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
s : out STD_LOGIC;
cout : out STD_LOGIC
);
end COMPONENT;
signal c : STD_LOGIC_VECTOR(6 downto 0);
begin
PROCESS (a,b,cin)
BEGIN
s(0) <= a(0) xor b(0) xor cin; --erstes s wird noch mit cin berechnet
c(0) <= (cin and b(0)) or (cin and a(0)) or (a(0) and b(0)); --sowie das erste cout
for i in 1 to 7 loop --Schleife um Stellen der Arrays durchzugehen
s(i) <= a(i) xor b(i) xor c(i-1);
c(i) <= (c(i-1) and b(i)) or (c(i-1) and a(i)) or (a(i) and b(i));
end loop;
cout <= c(6);
END PROCESS;
end Behavioral;
testbench I used:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity testbench_addierer is
-- Port ( );
end testbench_addierer;
architecture Behavioral of testbench_addierer is
SIGNAL a : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL b : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL cin : STD_LOGIC;
SIGNAL s : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL cout : STD_LOGIC;
COMPONENT addierer IS
PORT(
a : IN STD_LOGIC_VECTOR(7 downto 0);
b : IN STD_LOGIC_VECTOR(7 downto 0);
cin : IN STD_LOGIC;
s : OUT STD_LOGIC_VECTOR(7 downto 0);
cout: OUT STD_LOGIC
);
END COMPONENT;
begin
U1: addierer
PORT MAP(
a => a,
b => b,
cin => cin,
s => s,
cout => cout
);
process
begin
a <= "00000000" after 0ms;
a <= "00000001" after 10ms;
a <= "01010101" after 20ms;
b <= "00000000" after 0ms;
b <= "10001001" after 10ms;
b <= "00000001" after 20ms;
cin <= '0' after 0ms;
cin <= '0' after 10ms;
cin <= '0' after 20ms;
end process;
end Behavioral;
Thanks already and hmu if something's unclear in my code!!
(and pls keep in mind I'm an total beginner.. xD)
I am rather new (3 weeks) to VHDL, and I am having a problem in my latest assignment, which involves implementing overflow checking in a simple 4-bit adder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity add_sub_4bit is
Port ( a : in STD_LOGIC_VECTOR(3 downto 0);
b : inout STD_LOGIC_VECTOR(3 downto 0);
sel: in STD_LOGIC );
--sum : inout STD_LOGIC_VECTOR(3 downto 0)
end add_sub_4bit;
architecture Behavioral of add_sub_4bit is
signal localflow : STD_LOGIC;
signal localsum : STD_LOGIC_VECTOR (3 downto 0);
begin
localsum <= a + b when sel = '1'
else
a - b;
process(a,b,localsum) begin
if a(3) = '0' AND b(3) = '0' AND localsum(3) = '1' then
localflow <= '1';
elsif a(3) = '1' AND b(3) = '1' AND localsum(3) = '0' then
localflow <='1';
else
localflow <='0';
end if;
end process;
end Behavioral;
Now, the test cases are as such:
A=5, B=-3, giving 0 to sel adds them, 1 subtracts.
A=6, B=2, working much the same.
Now, given that the numbers are signed, of course, they are two's complement numbers, so is the result. However, I can only detect overflow in a case of adding 6 (0110) and 2 (0010), giving out -8 (1000), which is obviously an overflow case in 4-bit. But, when doing 5 -(-3), the result is much the same, 1000, but since I have given numbers of two different signs, I cannot detect overflow using my method.
My teacher has suggested that we change the sign of B depending on the value of sel - I tried something like making b <= b+"1000" based on that but that didn't help, and I don't know of other ways, being very new to the language. What can I do to get a proper program? Thank you.
Firstly:
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Don't do that. Especially if you want the numbers to be signed. Normal to use is:
use IEEE.numeric_std.all;
After that, you should cast the std_logic_vector to the wanted data type, e.g. 'signed', for the correct arithmetic.
Secondly, don't use inout. VHDL is not so good with bidirectional assignments. Either use in or out.
So combining the above, you could do (n.b. not the best code):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity add_sub_4bit is
Port (
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
sel: in STD_LOGIC;
sum : out STD_LOGIC_VECTOR(3 downto 0);
overflow : out std_logic
);
end add_sub_4bit;
architecture Behavioral of add_sub_4bit is
signal localflow : STD_LOGIC;
signal locala, localb, localsum : signed(4 downto 0); -- one bit more then input
signal sumout : std_logic_vector(4 downto 0);
begin
locala <= resize(signed(a), 5);
localb <= resize(signed(b), 5);
localsum <= locala + localb when sel = '1' else locala - localb;
-- overflow occurs when bit 3 is not equal to the sign bit(4)
localflow <= '1' when localsum(3) /= localsum(4) else '0';
-- convert outputs
sumout <= std_logic_vector(localsum);
--outputs
sum <= sumout(4)&sumout(2 downto 0);
overflow <= localflow;
end Behavioral;
You can test this using a testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity add_sub_4bit_tb is
end add_sub_4bit_tb;
architecture Behavioral of add_sub_4bit_tb is
signal sel : std_logic_vector(0 downto 0);
signal a, b, sum : std_logic_vector(3 downto 0);
begin
uut: entity work.add_sub_4bit
port map (a, b, sel(0), sum);
test: process
begin
for sel_o in 0 to 1 loop
sel <= std_logic_vector(to_signed(sel_o, 1));
for a_o in -8 to 7 loop
a <= std_logic_vector(to_signed(a_o, 4));
for b_o in -8 to 7 loop
b <= std_logic_vector(to_signed(b_o, 4));
wait for 1 ns;
end loop;
end loop;
end loop;
wait;
end process;
end Behavioral;
I'm trying to create an entity to fill an array from signals, but I'm getting the following error: near text "=" expecting "(" or " ' " or "."
This is my vhdl code
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.all;
entity decryptionarray is
port(
clk: in std_logic;
key_in: in std_logic_vector(7 downto 0);
encrypted_data : in std_logic_vector(127 downto 0);
encrypted_data_in : in std_logic_vector(127 downto 0);
decryption_key: out std_logic_vector(7 downto 0)
);
end entity decryptionarray;
architecture bhv of decryptionarray is
type deckeyarray is array (0 to 10) of std_logic_vector(127 downto 0);
signal dkey, keyin : std_logic_vector(7 downto 0);
signal edatain, edata : std_logic_vector(127 downto 0);
begin
P0:process(clk) is
begin
if(deckeyarray(10)/=null) then
for j in 0 to 10 loop
deckeyarray(j)=null;
end loop;
else
keyin <= key_in;
edata <= encrypted_data;
edatain <= encrypted_data_in ;
dkey <= decryption_key ;
end if;
end process P0;
end architecture bhv;
VHDL does not have compare with null as in deckeyarray(10)/=null, and deckeyarray is a type, not a signal.
To check for all 0's you can do:
use ieee.numeric_std.all;
...
type deckeyarray_t is array (0 to 10) of std_logic_vector(127 downto 0);
signal deckeyarray : deckeyarray_t;
...
if unsigned(deckeyarray(10)) = 0 then
The compare can also be made without the unsigned and numeric_std, but using deckeyarray(10) = (deckeyarray(10)'range => '0') instead.
To fill with all 0's you can do:
deckeyarray(j) <= (others => '0');
Note that the decryption_key output port is read in dkey <= decryption_key;, which does not make sense.
I am just trying to make a simple two's complement device in VHDL but it is throwing back this really annoying error and I'm unsure what I have done wrong. Probably something very silly...The error is
"Error (10327): VHDL error at twocompliment.vhd(21): can't determine definition of operator ""nand"" -- found 0 possible definitions"
The code is
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity twoscompliment is
generic
(
Nbits : positive := 8
);
port
(
--Inputs
A : in std_logic_vector (Nbits-1 downto 0);
--Outputs
Y : out std_logic_vector (Nbits downto 0)
);
end twoscompliment;
architecture twoscompliment_v1 of twoscompliment is
begin
Y <= std_logic_vector(unsigned(A NAND '1') + '1');
end twoscompliment_v1;
Any help would be awesome!
It seems to me you are trying to negate the input number... Maybe I'm missing something vital, but the other answers give a solution which, whilst achieving the goal, appear to be one step more obfuscated than they need to be.
Barring the ugly conversions, what's wrong with
y <= std_logic_vector(-signed(resize(unsigned(A)), y'length));
Of course, I would argue that if A and Y are supposed to be representing signed numbers (or unsigned numbers), they should be expressed as such:
library ieee;
use ieee.numeric_std.all;
entity twoscomplement is
generic
(
Nbits : positive := 8
);
port
(
A : in unsigned (Nbits-1 downto 0);
Y : out signed (Nbits downto 0)
);
end entity twoscomplement;
architecture a1 of twoscomplement is
begin
Y <= -signed(resize(A, Y'length));
end architecture;
Let's check the results:
entity test_twoscomplement is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of test_twoscomplement is
signal A : unsigned (7 downto 0);
signal Y : signed(8 downto 0);
begin
dut : entity work.twoscomplement port map (A => A, Y=>Y);
process
begin
for i in 0 to 255 loop
A <= to_unsigned(i, A'length);
wait for 1 ns;
assert to_integer(Y) = -i severity error;
end loop;
report "tests done";
wait;
end process;
end architecture;
Running with GHDL:
$ ghdl -a twoscomp.vhd
$ ghdl --elab-run test_twoscomplement
twoscomp.vhd:40:8:#256ns:(report note): tests done
Success!
Try this:
architecture twoscompliment_v1 of twoscompliment is
signal temp : std_logic_vector(Nbits-1 downto 0);
begin
temp <= not A;
Y <= std_logic_vector(unsigned(temp + 1));
end twoscompliment_v1;
architecture twoscompliment_v1 of twoscompliment is
constant ONE: UNSIGNED(Y'RANGE) := (0 => '1', others => '0');
begin
Y <= std_logic_vector(unsigned (not A) + ONE);
end twoscompliment_v1;
Hi gentleman basically 2's complement is done by inverting the binary bits of a
given no. i.e changing ones to zeroes and zeroes to ones, after that add the
binary bit '1' to the Least significant bit of the given binary number. Now I
have a program
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity twoscomplementconversion is Port (
bin : in STD_LOGIC_VECTOR (3 downto 0);
twos : out STD_LOGIC_VECTOR (3 downto 0)
);
end twoscomplementconversion;
architecture Behavioral of twoscomplementconversion is
component fourbitadder45 Port (
a : in std_logic_vector (3 downto 0);
b : in std_logic_vector(3 downto 0);
cin : in std_logic;
cout : out std_logic;
sum : out std_logic_vector (3 downto 0)
);
end component;
signal onebit : std_logic_vector(3 downto 0):="0001";
signal cin1 : std_logic:='0';
signal notbin : std_logic_vector(3 downto 0);
signal cout1 : std_logic;
begin
notbin <= not(bin);
twos1: fourbitadder45 port map (
a => notbin,
b => onebit,
cin => cin1,
cout => cout1,
sum => twos
);
end Behavioral;
The four bit adder program is given below:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity fourbitadder45 is Port (
a : in std_logic_vector (3 downto 0);
b : in std_logic_vector(3 downto 0);
cin : in std_logic;
cout : out std_logic;
sum : out std_logic_vector (3 downto 0)
);
end fourbitadder45;
architecture Behavioral of fourbitadder45 is
component fulladder2 Port (
a : in std_logic;
b : in std_logic;
cin : in std_logic;
cout : out std_logic;
sum : out std_logic
);
end component;
signal c:std_logic_vector (3 downto 1);
begin
fa1 :fulladder2 port map (a => a(0), b => b(0), cin => cin, cout => c(1), sum => sum(0));
fa2 :fulladder2 port map (a => a(1), b => b(1), cin => c(1), cout => c(2), sum => sum(1));
fa3 :fulladder2 port map (a => a(2), b => b(2), cin => c(2), cout => c(3), sum => sum(2));
fa4 :fulladder2 port map (a => a(3), b => b(3), cin => c(3), cout => cout, sum => sum(3));
end Behavioral;
four bit adder contains 4 full adders so the full adder program is given below:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladder2 is Port (
a : in std_logic;
b : in std_logic;
cin : in std_logic;
cout : out std_logic;
sum : out std_logic
);
end fulladder2;
architecture Behavioral of fulladder2 is
begin
sum <= a xor b xor cin;
cout <= ((a and b) or (b and cin) or (cin and a));
end Behavioral;
I hope that answers the question. This is a method there are many different methods