I am making a FSM Moore sequence detector on VHDL for a given input bit sequence (10100110) but now I also want to add an even parity bit to the input bit sequence as a new sequence. I know the logic behind it to use xor gate but im unable to implement it in the code.
This is my design code:
library IEEE;
use IEEE.std_logic_1164.all;
entity sequence_detector is
port(clock: in std_logic;
input_seq: in std_logic;
detector: out std_logic);
end sequence_detector;
architecture behaviour of sequence_detector is
type state is (init, s1, s2, s3, s4);
signal p_s, n_s : state;
begin
process
begin
wait until clock'event and clock = '1';
p_s <= n_s;
end process;
process (input_seq, p_s)
begin
case(p_s) is
when init =>
if(input_seq = '1') then
n_s <= s1;
detector <= '0';
else
n_s <= init;
detector <= '0';
end if;
when s1 =>
if(input_seq = '0') then
n_s <= s2;
detector <= '0';
else
n_s <= s1;
detector <= '0';
end if;
when s2 =>
if(input_seq = '0') then
n_s <= s3;
detector <= '0';
else
n_s <= s1;
detector <= '0';
end if;
when s3 =>
if(input_seq = '1') then
n_s <= s4;
detector <= '0';
else
n_s <= init;
detector <= '0';
end if;
when s4 => --here we decide if its overlapping or not
if(input_seq = '1') then
n_s <= s1;
detector <= '1';
else
n_s <= s2;
detector <= '0';
end if;
end case;
end process;
end behaviour;
This is my testbench:
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench is
end testbench;
architecture behaviour of testbench is
component sequence_detector is
port(clock: in std_logic;
input_seq: in std_logic;
detector: out std_logic);
end component;
signal clock, input_seq : std_logic;
signal detector : std_logic;
constant clock_period: Time := 10 ns;
begin
DUT: sequence_detector port map(clock, input_seq, detector);
p_clock: process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
process
begin
input_seq <= '1';
wait for 10 ns;
input_seq <= '0';
wait for 10 ns;
input_seq <= '1';
wait for 20 ns;
input_seq <= '0';
wait for 20 ns;
input_seq <= '1';
wait for 20 ns;
input_seq <= '0';
wait;
end process;
end behaviour;
This is the output:
output graph
Related
I'm running the code in edaplayground because that's the required site we should use.
this is my vhdl code idk why it doesnt work:
-- Testbench for the counter design
entity counter_tb is
end entity;
architecture sim of counter_tb is
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal count : std_logic_vector(2 downto 0);
begin
-- Instantiate the design under test
dut: entity work.counter
port map (
clk => clk,
reset => reset,
count => count
);
-- Clock process to generate a clock signal
clk_process : process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
-- Stimulus process to reset the counter and generate test sequences
stim_process : process
begin
wait for 10 ns;
reset <= '1';
wait for 5 ns;
reset <= '0';
wait for 10 ns;
assert count = "000";
wait for 10 ns;
assert count = "001";
wait for 10 ns;
assert count = "011";
wait for 10 ns;
assert count = "110";
wait for 10 ns;
assert count = "111" ;
wait for 10 ns;
assert count = "000";
end process;
end
the design:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity counter is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
count : out STD_LOGIC_VECTIC(2 downto 0));
end counter;
architecture Behavioral of counter is
type states is (s0, s1, s3, s6, s7);
signal current_state, next_state : states;
begin
process(clk, reset)
begin
if reset = '1' then
current_state <= s0;
elsif rising_edge(clk) then
current_state <= next_state;
end if;
end process;
count <= "000" when current_state = s0 else
"001" when current_state = s1 else
"011" when current_state = s3 else
"110" when current_state = s6 else
"111" when current_state = s7;
next_state <= s1 when current_state = s0 else
s3 when current_state = s1 else
s6 when current_state = s3 else
s7 when current_state = s6 else
s0 when current_state = s7;
end Behavioral;
i tried searching on youtube but i still cant fix it also i tried following the ims our prof gave us but still cant fix it. what i need to do is to make the count like 0 1 3 6 7 0 1 ... in the ep wave
I am fairly new to VHDL and am following this tutorial to implement the following Mealy Finite State Machine:
and have written the following code in VHDL:
library ieee;
use ieee.std_logic_1164.all;
entity fsm is
port(clk, rst, in1 : in std_logic; o1 : out std_logic);
end fsm;
architecture mealy of fsm is
type state is (state1, state2);
signal current_state, next_state : state;
begin
comb: process(current_state, in1) begin
next_state <= current_state; -- default case
case current_state is
when state1 =>
o1 <= '0';
if in1 = '1' then
o1 <= '1';
next_state <= state2;
end if;
when state2 =>
o1 <= '1';
if in1 = '0' then
o1 <= '0';
next_state <= state1;
end if;
end case;
end process;
mem: process(clk, rst) begin
if rst = '1' then
current_state <= state1;
else
current_state <= next_state;
end if;
end process;
end mealy;
However on applying the following testbench:
library ieee;
use ieee.std_logic_1164.all;
entity fsm_tb is
end fsm_tb;
architecture sim of fsm_tb is
constant clockperiod : time := 10 ns; -- 100 Mhz clock
signal clk : std_logic := '0';
signal rst : std_logic;
signal in1, o_mealy : std_logic;
begin
uut_mealy : entity work.fsm(mealy) port map( clk => clk, rst => rst, in1 => in1, o1 => o_mealy);
clk <= not clk after clockperiod/2;
process begin
-- initial reset
in1 <= '0';
rst <= '1';
wait until rising_edge(clk);
-- take device out of reset
rst <= '0';
-- apply same inputs to both the devices
in1 <= '0'; wait for 23 ns;
in1 <= '1'; wait for 32 ns;
in1 <= '0'; wait for 7 ns;
in1 <= '1'; wait for 15 ns;
wait;
end process;
end sim;
the waveforms that I have obtained do not make sense to me:
As you can see the output o_mealy changes even without clock edge. It simply seems to only be following the input. By contrast, I have implemented the equivalent Moore machine and it seems to be working just fine:
If anyone can point out what I am doing wrong, it would be highly appreciated. Again, I have used this video for reference. I am using GHDL with GTKWave.
Taking a look at your concurrent logic:
case current_state is
when state1 =>
o1 <= '0';
if in1 = '1' then
o1 <= '1';
next_state <= state2;
end if;
when state2 =>
o1 <= '1';
if in1 = '0' then
o1 <= '0';
next_state <= state1;
end if;
end case;
In any of the two states, if in1 = '1', the output is 1, if in1 = '0' the output is 0. So the FSM works fine, but looking from the outside in you just cannot see the difference between the two states.
In terms of what are you doing wrong: I think this is correct, actually, looking at your drawing. In a mealy machine, the output is depended on the current state and the current input, which is exactly what is happening here.
Using GHDL's GHW dump file format to allow gtkwave to display enumerated type values we see:
where in current_state is being updated on both edges of clock (in a manner not likely supported for synthesis).
That can be corrected by evaluating a single clock edge in a manner conducive to synthesis:
mem: process(clk, rst) begin
if rst = '1' then
current_state <= state1;
elsif rising_edge(clk) then -- evaluate clock edge
current_state <= next_state;
end if;
end process;
And that gives us
current_state transitioning on one clock edge only.
I am trying to write a program to detect if a given input is a prime number or not. When I run the test bench I get correct results however when I run it on the FPGA it only recognizes numbers that are divisible 3 or even as not prime. Any number such as 25 which is divisible by 5 will result in isPrime being 1. What could be causing this inconsistent result?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
entity PrimeNumber is
Port ( clk: in std_logic;
rst : in std_logic;
input: in std_logic_vector(15 downto 0);
isPrime: out std_logic:= '0';
testOut: out std_logic_vector(31 downto 0)
);
end PrimeNumber;
architecture Behavioral of PrimeNumber is
SIGNAL current_state: std_logic_vector(2 downto 0);
signal next_state: std_logic_vector(2 downto 0):= "000";
signal max: integer;
signal temp: integer;
signal x: integer;
signal nextX:integer;
signal localPrime : std_logic:= '0';
signal current : integer;
signal update: std_logic := '0';
begin
nextX <= x +2;
process(current_state,input)
begin
case (current_state) is
when "000" => --Initial State
update <= '0';
localPrime <= '0';
if(input < x"0004")then
next_state <= "111";
else
max <= to_integer(unsigned(input(15 downto 1)));
current <=to_integer(unsigned(input));
if(input(0) = '0')then
next_state <= "110";
else
next_state <= "001";
end if;
end if;
when "001" => -- Computation State
localPrime <= '0';
temp <= current mod x;
if(x > max) then
next_state <= "111";
else
next_state <= "010";
end if;
update <= '1';
when "010" => -- Checking State
update <= '0';
localPrime <= '0';
if(temp = 0) then
next_state <= "110";
else
next_state <= "001";
end if;
when "110" =>
localPrime <= '0'; -- Not Prime State
next_state <= "110";
when "111" =>
update <= '0';
localPrime <= '1'; --Prime State
next_state <= "111";
when others =>
temp <= 0;
localPrime <= '0';
next_state <= "000";
end case;
end process;
Update_Registers: process(clk)
begin
if(clk'event and clk = '1') then
if ( rst = '1') then
current_state <= "000";
isPrime <= '0';
x<=3;
else
if(update = '1') then
x <= nextX;
end if;
current_state <= next_state;
isPrime <= localPrime;
end if;
end if;
end process;
end Behavioral;
To quickly check sim/syn mismatch, with the visibility you need outside of HW: output the mod result to a port, sim, should still "work"... syn, compile your (hopefully, verilog) netlist for TB, point to compiled netlist, sim, check the mod result against RTL/expected results.
I have created a bit sequence detector (for sequence 1110) using VHDL. I have used Moore’s State Machine to accomplish the task.
I am able to compile my code and get the desired output.
But on the FPGA board I am supposed to use SW0 as clock, SW1 as data input, SW2 as RESET, any of the LED as data output.
The problems I am facing:
I am unable to assign the clock signal to a switch, I always get an error. So I assigned the clock signal to the default clock signal on the board i.e. LOC = "E3" it work fine. But according to my question I need to assign it to a switch. How do do that?
I am unable to show the output on the fpga board i.e. the led lights up too fast for the naked eye once the data in pin is applied. Any suggestion on how to display the output using 3 input switch and an LED as output as per the above question?
The following code is my design implementation:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Design is
Port ( clock : in STD_LOGIC;
din : in STD_LOGIC;
rst : in STD_LOGIC;
dout : out STD_LOGIC);
end Design;
architecture Behavioral of Design is
type state is (st0, st1, st2, st3, st4);
signal present_state, next_state : state;
begin
synchronous_process: process (clock)
begin
if rising_edge(clock) then
if (rst = '1') then
present_state <= st0;
else
present_state <= next_state;
end if;
end if;
end process;
output_decoder : process(present_state, din)
begin
next_state <= st0;
case (present_state) is
when st0 =>
if (din = '1') then
next_state <= st1;
else
next_state <= st0;
end if;
when st1 =>
if (din = '1') then
next_state <= st2;
else
next_state <= st0;
end if;
when st2 =>
if (din = '1') then
next_state <= st3;
else
next_state <= st0;
end if;
when st3 =>
if (din = '1') then
next_state <= st3;
else
next_state <= st4;
end if;
when st4 =>
if (din = '1') then
next_state <= st1;
else
next_state <= st0;
end if;
when others =>
next_state <= st0;
end case;
end process;
next_state_decoder : process(present_state)
begin
case (present_state) is
when st0 =>
dout <= '0';
when st1 =>
dout <= '0';
when st2 =>
dout <= '0';
when st3 =>
dout <= '0';
when st4 =>
dout <= '1';
when others =>
dout <= '0';
end case;
end process;
end Behavioral;
The following is my testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_moore is
end tb_moore;
architecture Behavioral of tb_moore is
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Design
PORT(
clock : IN std_logic;
din : IN std_logic;
rst : IN std_logic;
dout : OUT std_logic
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal din : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal dout : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Design PORT MAP (
clock => clock,
din => din,
rst => rst,
dout => dout
);
-- Clock process definitions
clk_process :process
begin
clock <= '0';
wait for clk_period/2;
clock <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 20 ns;
rst <= '0';
din <= '1';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '0';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '1';
end process;
END;
and the following is the constrains file i used for the Nexys DDR4 FPGA Board.
## Clock signal
NET "clock" LOC = "E3" | IOSTANDARD = "LVCMOS33";
## Switches
NET "din" LOC=L16 | IOSTANDARD=LVCMOS33;
NET "rst" LOC=M13 | IOSTANDARD=LVCMOS33;
## LEDs
NET "dout" LOC=H17 | IOSTANDARD=LVCMOS33;
Process 2 keeps getting activated when there isn't a change. I have a board to test my code, and the state will change when I flip the clock(I set the clock as a button). In my code, the state will only change if I flip Qin. So it isn't doing what I wish it to do, and I spent a lot of time trying to find out what's causing it, but I can't. Please help.
This is the testbench graph TESTBENCH GRAPH
As you can see, in the graph, the output of the PS(present_state) is correct, but in the board, it isn't output right. There is one thing I found that is really important, I tried to output next_state on board, when I flip Qin to '1', the state shows "001", and then I flip clk to '1', the state become "010", which is not suppose to happen. I hope this is an important information.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity VendingMechine is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Cr : in STD_LOGIC;
Qin : in STD_LOGIC;
S : in STD_LOGIC;
CB : in STD_LOGIC;
W : in STD_LOGIC;
CRo : out STD_LOGIC_VECTOR(1 DOWNTO 0);
Qo : out STD_LOGIC;
PS : out STD_LOGIC_VECTOR(2 DOWNTO 0);
Wo : out STD_LOGIC;
CBo : out STD_LOGIC;
So : out STD_LOGIC);
end VendingMechine;
architecture Behavioral of VendingMechine is
TYPE state IS(Idle, S1, S2, S3, Soda, Candy, Water);
Signal Next_State : state;
Signal Present_State : state := Idle;
begin
Process1:Process(clk, reset)
begin
if(reset = '1') THEN
Present_State <= Idle;
elsif rising_edge(clk) THEN Present_State <= Next_State;
end if;
end process;
Process2:Process(Qin, Present_State, Cr, S, w)
begin
Next_State <= Present_State;
CRo <= "00"; Qo <= '0'; PS <= "000"; Wo <= '0'; CBo <= '0'; So <= '0';
CASE Present_State IS
When Idle =>
PS <= "000";
if Qin='1' Then Next_State <= S1;
else Next_State <= Idle;
end if;
When S1 =>
PS <= "001";
if Qin='1' Then Next_State <= S2;
elsif Cr = '1' Then Cro <= "01"; Next_State <= Idle;
else Next_State <= S1;
end if;
When S2 =>
PS <= "010";
if Qin='1' Then Next_State <= S3;
elsif Cr = '1' Then CRo <="10"; Next_State <= Idle;
elsif S = '1' Then Next_State <= Soda;
elsif CB = '1' Then Next_State <= Candy;
else Next_State <= S2;
end if;
When S3 =>
PS <= "011";
if Cr = '1' Then CRo <= "11"; Next_State <= Idle;
elsif S = '1' Then Qo <= '1'; Next_State <= Soda;
elsif CB = '1' Then Qo <= '1'; Next_State <= Candy;
elsif W = '1' Then Next_State <= Water;
elsif Qin = '1' Then Qo <= '1';
else Next_State <= S3;
end if;
When Soda =>
PS <= "100";
So <= '1';
Next_State <= Idle;
When Candy =>
PS <= "101";
CBo <= '1';
Next_State <= Idle;
When Water =>
PS <= "110";
Wo <= '1';
Next_State <= Idle;
END CASE;
end process;
end Behavioral;
Process will launch not only when signals changes, but every time you assign something to signal, even if it has same value as before. That may be the reason. In parallel process you can't rely on times launch, but on result in case of some conditions, that came in inputs.
Is Qin connected to an external switch? If yes, you should implement clock-domain synchronization (and possible debouncing) on the inputs.
Please let me know in the comments if you don't know how.
Lack of clock-synchronous signals will cause glitches and thus hang-ups in the state-machine. Lack of debouncing will cause multiple switch pulses ("bouncing")