I'm running the code in edaplayground because that's the required site we should use.
this is my vhdl code idk why it doesnt work:
-- Testbench for the counter design
entity counter_tb is
end entity;
architecture sim of counter_tb is
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal count : std_logic_vector(2 downto 0);
begin
-- Instantiate the design under test
dut: entity work.counter
port map (
clk => clk,
reset => reset,
count => count
);
-- Clock process to generate a clock signal
clk_process : process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
-- Stimulus process to reset the counter and generate test sequences
stim_process : process
begin
wait for 10 ns;
reset <= '1';
wait for 5 ns;
reset <= '0';
wait for 10 ns;
assert count = "000";
wait for 10 ns;
assert count = "001";
wait for 10 ns;
assert count = "011";
wait for 10 ns;
assert count = "110";
wait for 10 ns;
assert count = "111" ;
wait for 10 ns;
assert count = "000";
end process;
end
the design:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity counter is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
count : out STD_LOGIC_VECTIC(2 downto 0));
end counter;
architecture Behavioral of counter is
type states is (s0, s1, s3, s6, s7);
signal current_state, next_state : states;
begin
process(clk, reset)
begin
if reset = '1' then
current_state <= s0;
elsif rising_edge(clk) then
current_state <= next_state;
end if;
end process;
count <= "000" when current_state = s0 else
"001" when current_state = s1 else
"011" when current_state = s3 else
"110" when current_state = s6 else
"111" when current_state = s7;
next_state <= s1 when current_state = s0 else
s3 when current_state = s1 else
s6 when current_state = s3 else
s7 when current_state = s6 else
s0 when current_state = s7;
end Behavioral;
i tried searching on youtube but i still cant fix it also i tried following the ims our prof gave us but still cant fix it. what i need to do is to make the count like 0 1 3 6 7 0 1 ... in the ep wave
Related
Please forgive myself if you will find some trivial errors in my code .. I'm still a beginner with VHDL.
Well, I have to deal with a serial interface from an ADC. The interface is quite simple ... there is a wire for the serial data (a frame of 24 bits), a signal DRDY that tells me when the new sample data is available and a serial clock (SCLK) that push the bit into (rising edge). Everything is running continuously...
I need to capture correctly the 24 bit of the sample, put them on a parallel bus (shift register) and provide a "data valid" signal for the blocks that will process the samples ...
Due to the fact that my system clock is x4 the frequency of the serial interface, i was thinking that doing the job with a FSM will be easy ...
When you look into the code you will see a process to capture the rising edges of the DRDY and SCLK.
Then a FSM with few states (Init, wait_drdy, wait_sclk, inc_count, check_count).
I use a counter (cnt unsigned) to check if I've already captured the 24 bits, using also to redirect the states of the FSM in "check_count" state.
Here a picture:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity serial_ads1675 is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk : in std_logic;
sdata : in std_logic;
drdy : in std_logic;
pdata : out std_logic_vector(23 downto 0);
pdready : out std_logic
);
end serial_ads1675;
architecture Behavioral of serial_ads1675 is
-- Internal declarations
signal ipdata : std_logic_vector (23 downto 0);
signal ipdready : std_logic;
signal tmp1, tmp2, tmp3, tmp4 : std_logic;
signal rise_drdy, rise_sclk : std_logic;
signal cnt : unsigned (4 downto 0);
type state is (init, wait_drdy, wait_sclk, inc_count, check_count);
signal actual_state, next_state : state;
begin
-- Concurrent statements
pdata <= ipdata;
pdready <= ipdready;
rise_drdy <= '1' when ((tmp1 = '1') and (tmp2 = '0')) else '0';
rise_sclk <= '1' when ((tmp3 = '1') and (tmp4 = '0')) else '0';
-- Process
process (clk, reset)
begin
if(reset = '0') then
tmp1 <= '0';
tmp2 <= '0';
tmp3 <= '0';
tmp4 <= '0';
elsif (falling_edge(clk)) then
tmp1 <= drdy;
tmp2 <= tmp1;
tmp3 <= sclk;
tmp4 <= tmp3;
end if;
end process;
process (reset, clk)
begin
if (reset = '0') then
actual_state <= init;
elsif (rising_edge(clk)) then
actual_state <= next_state;
end if;
end process;
process (rise_sclk, rise_drdy) -- Next State affectation
begin
case actual_state is
when init =>
next_state <= wait_drdy;
ipdata <= (others => '0');
ipdready <= '0';
cnt <= (others => '0');
when wait_drdy =>
if (rise_drdy = '0') then
next_state <= actual_state;
else
next_state <= wait_sclk;
end if;
cnt <= (others => '0');
when wait_sclk =>
if (rise_sclk = '0') then
next_state <= actual_state;
else
next_state <= inc_count;
end if;
ipdready <= '0';
when inc_count =>
next_state <= check_count;
cnt <= cnt + 1;
ipdready <= '0';
ipdata(23 downto 1) <= ipdata(22 downto 0);
ipdata(0) <= sdata;
when check_count =>
case cnt is
when "11000" =>
next_state <= wait_drdy;
ipdready <= '1';
when others =>
next_state <= wait_sclk;
ipdready <= '0';
end case;
when others =>
next_state <= init;
end case;
end process;
end Behavioral;
My problem is during the check_count state ...
I'm expecting that this state should last one system clock cycle, but actually it last much more.
Here a snapshot of the behavioral simulation:
Due to the fact that this state last more than expected, i miss the following SCLK pulse and don't record the next bit ...
I don't understand why this state last so many system clock cycles instead of just one ...
Anyone has some clues and bring some light in my dark night ?
Thanks in advance.
Edit: I've tried to change the signal cnt for an integer variable internal to the process of the FSM ... Same results
The error is this:
process (rise_sclk, rise_drdy) -- Next State affectation
begin
-- code omitted, but does generally this:
next_state <= SOME_VALUE;
end process;
Because the sensitivity list includes only the signals rise_sclk and rise_drdy, the process is "executed" only if any of these signals changes. You can follow this in the wave diagram.
You don't have a synchronous design running on clk. Put clk on the sensitivity list and base the decisions on the levels of rise_sclk and rise_drdy. As an excerpt:
process (clk) -- Next State affectation
begin
if rising_edge(clk) then
case actual_state is
when init =>
next_state <= wait_drdy;
-- and so on
end case;
end if;
end process;
I am making a FSM Moore sequence detector on VHDL for a given input bit sequence (10100110) but now I also want to add an even parity bit to the input bit sequence as a new sequence. I know the logic behind it to use xor gate but im unable to implement it in the code.
This is my design code:
library IEEE;
use IEEE.std_logic_1164.all;
entity sequence_detector is
port(clock: in std_logic;
input_seq: in std_logic;
detector: out std_logic);
end sequence_detector;
architecture behaviour of sequence_detector is
type state is (init, s1, s2, s3, s4);
signal p_s, n_s : state;
begin
process
begin
wait until clock'event and clock = '1';
p_s <= n_s;
end process;
process (input_seq, p_s)
begin
case(p_s) is
when init =>
if(input_seq = '1') then
n_s <= s1;
detector <= '0';
else
n_s <= init;
detector <= '0';
end if;
when s1 =>
if(input_seq = '0') then
n_s <= s2;
detector <= '0';
else
n_s <= s1;
detector <= '0';
end if;
when s2 =>
if(input_seq = '0') then
n_s <= s3;
detector <= '0';
else
n_s <= s1;
detector <= '0';
end if;
when s3 =>
if(input_seq = '1') then
n_s <= s4;
detector <= '0';
else
n_s <= init;
detector <= '0';
end if;
when s4 => --here we decide if its overlapping or not
if(input_seq = '1') then
n_s <= s1;
detector <= '1';
else
n_s <= s2;
detector <= '0';
end if;
end case;
end process;
end behaviour;
This is my testbench:
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench is
end testbench;
architecture behaviour of testbench is
component sequence_detector is
port(clock: in std_logic;
input_seq: in std_logic;
detector: out std_logic);
end component;
signal clock, input_seq : std_logic;
signal detector : std_logic;
constant clock_period: Time := 10 ns;
begin
DUT: sequence_detector port map(clock, input_seq, detector);
p_clock: process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
process
begin
input_seq <= '1';
wait for 10 ns;
input_seq <= '0';
wait for 10 ns;
input_seq <= '1';
wait for 20 ns;
input_seq <= '0';
wait for 20 ns;
input_seq <= '1';
wait for 20 ns;
input_seq <= '0';
wait;
end process;
end behaviour;
This is the output:
output graph
I have created a bit sequence detector (for sequence 1110) using VHDL. I have used Moore’s State Machine to accomplish the task.
I am able to compile my code and get the desired output.
But on the FPGA board I am supposed to use SW0 as clock, SW1 as data input, SW2 as RESET, any of the LED as data output.
The problems I am facing:
I am unable to assign the clock signal to a switch, I always get an error. So I assigned the clock signal to the default clock signal on the board i.e. LOC = "E3" it work fine. But according to my question I need to assign it to a switch. How do do that?
I am unable to show the output on the fpga board i.e. the led lights up too fast for the naked eye once the data in pin is applied. Any suggestion on how to display the output using 3 input switch and an LED as output as per the above question?
The following code is my design implementation:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Design is
Port ( clock : in STD_LOGIC;
din : in STD_LOGIC;
rst : in STD_LOGIC;
dout : out STD_LOGIC);
end Design;
architecture Behavioral of Design is
type state is (st0, st1, st2, st3, st4);
signal present_state, next_state : state;
begin
synchronous_process: process (clock)
begin
if rising_edge(clock) then
if (rst = '1') then
present_state <= st0;
else
present_state <= next_state;
end if;
end if;
end process;
output_decoder : process(present_state, din)
begin
next_state <= st0;
case (present_state) is
when st0 =>
if (din = '1') then
next_state <= st1;
else
next_state <= st0;
end if;
when st1 =>
if (din = '1') then
next_state <= st2;
else
next_state <= st0;
end if;
when st2 =>
if (din = '1') then
next_state <= st3;
else
next_state <= st0;
end if;
when st3 =>
if (din = '1') then
next_state <= st3;
else
next_state <= st4;
end if;
when st4 =>
if (din = '1') then
next_state <= st1;
else
next_state <= st0;
end if;
when others =>
next_state <= st0;
end case;
end process;
next_state_decoder : process(present_state)
begin
case (present_state) is
when st0 =>
dout <= '0';
when st1 =>
dout <= '0';
when st2 =>
dout <= '0';
when st3 =>
dout <= '0';
when st4 =>
dout <= '1';
when others =>
dout <= '0';
end case;
end process;
end Behavioral;
The following is my testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_moore is
end tb_moore;
architecture Behavioral of tb_moore is
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Design
PORT(
clock : IN std_logic;
din : IN std_logic;
rst : IN std_logic;
dout : OUT std_logic
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal din : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal dout : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Design PORT MAP (
clock => clock,
din => din,
rst => rst,
dout => dout
);
-- Clock process definitions
clk_process :process
begin
clock <= '0';
wait for clk_period/2;
clock <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 20 ns;
rst <= '0';
din <= '1';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '0';
wait for 20 ns;
din <= '1';
wait for 20 ns;
din <= '1';
end process;
END;
and the following is the constrains file i used for the Nexys DDR4 FPGA Board.
## Clock signal
NET "clock" LOC = "E3" | IOSTANDARD = "LVCMOS33";
## Switches
NET "din" LOC=L16 | IOSTANDARD=LVCMOS33;
NET "rst" LOC=M13 | IOSTANDARD=LVCMOS33;
## LEDs
NET "dout" LOC=H17 | IOSTANDARD=LVCMOS33;
I'm sending data to and A/D converter and I need the command data to be delayed at least 50ns from clk_19khz. Here is what I have so far.
How do I insert a delay of 50ns which is a requirement for the A/D between the clk_19khz and my first Dout bit to the A/D?
I'm using a Xilinx FPGA. Thanks for the help!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PSOL is
Port ( clk : in STD_LOGIC;
clk_19khz : OUT std_logic;
Dout :out std_logic);
end PSOL;
architecture Behavioral of PSOL is
signal temp : std_logic;
signal count : integer range 0 to 1301 := 0; --1301
signal temp2 : std_logic;
signal dcount : integer range 0 to 11 := 0; --
signal start : std_logic := '1'; -- indicates the start of
signal parity : std_logic := '1'; --used to varify data sent
signal stop : std_logic := '0'; --indicate when word/command has
--signal chip_select : bit :='1'; -- active low
begin
process (clk)
begin
if (clk' EVENT AND clk='1') then
if (count = 1301) then --1301
temp <= not(temp);
count <=0;
else
count <= count + 1;
end if;
end if;
end process;
clk_19khz <= temp;
temp2 <= temp;
process (temp2)
begin
If (temp2' EVENT and temp2 ='0') then
dcount <= dcount + 1;
parity <= '1';
stop <= '0';
start <='1';
if (dcount < 12 and start = '1' and stop = '0') then
CASE dcount is
when 1 => Dout <= start; -- need delay 50ns before this
when 2 => Dout <= '0';
when 3 => Dout <= '1';
when 4 => Dout <= '0';
when 5 => Dout <= '1';
when 6 => Dout <= '0';
when 7 => Dout <= '0';
when 8 => Dout <= '1';
when 9 => Dout <= '1';
when 10 => Dout <= parity;
when 11 => Dout <= '0';
when others => null;
end case;
end if;
end if;
--dcount <= 0;
--start <='1';
end process;
end Behavioral;
Your clock (50 MHz) has a period of 20 ns. So you'll need a modulo-3 counter to count a delay of at least 3 clock pulses which gives a delay of 60 ns.
Declarations:
signal delay_en : std_logic;
signal delay_us : unsigned(1 downto 0) := (others => '0');
signal delay_ov : std_logic;
Usage:
process(clk)
begin
if rising_edge(clk) then
if (delay_en = '1') then
delay_us <= delay_us + 1;
else
delay_us <= (others => '0');
end if;
end if;
end process;
delay_ov <= '1' when (delay_us = 2) else '0';
Your current implementation needs to drive delay_en while it's waiting for the timespan. If the delay is over, it emits the signal delay_ov (ov = overflow). This can be used by your solution to go on the in algorithm. Your code should also deassert delay_en, what clears the counter to 0.
I am attempting to build a counter in VHDL. Eventual goal is to hook the "do_count" to a button. The total will be converted to BCD and displayed on a 7-segment display. Push the button, watch the numbers increment.
I'm using ModelSim and I can see the internal "counter_value" correctly increment by 1. But the output signal "total" becomes "000X" then "00X0" during my two test "do_count"s. Why am I getting an X'd signal?
I've moved the "output <= current_value" around inside the process, outside the process, inside the 'if's, etc. Still the "000X".
I've tried using a variable 'tmp' inside the process.
count_up : process(clk) is
variable tmp : unsigned (15 downto 0 );
begin
tmp := current_value;
-- snip
if do_count='1' then
current_value <= tmp + to_unsigned(1,16);
end if;
Still I get the "000X".
Full code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity d_counter is
port ( rst : in std_logic;
clk : in std_logic;
do_count : in std_logic;
total : out unsigned (15 downto 0)
);
end entity d_counter;
architecture counter_arch of d_counter is
signal current_value : unsigned (15 downto 0) := (others=>'0');
begin
count_up : process(clk) is
begin
if rst='1' then
current_value <= (others=>'0');
total <= (others=>'0');
elsif rising_edge(clk) then
if do_count='1' then
current_value <= current_value + to_unsigned(1,16);
end if;
end if;
end process count_up;
total <= current_value;
end architecture counter_arch;
Testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity test_counter is
begin
end entity test_counter;
architecture run_test_counter of test_counter is
signal t_rst : std_logic := '1';
signal t_clk : std_logic := '0';
signal t_do_count : std_logic;
signal t_total : unsigned( 15 downto 0 );
component d_counter is
port ( rst : in std_logic;
clk : in std_logic;
do_count : in std_logic;
total : out unsigned( 15 downto 0 )
);
end component d_counter;
begin
uut : d_counter
port map( rst => t_rst,
clk => t_clk,
do_count => t_do_count,
total => t_total );
clock : process is
begin
t_clk <= '0'; wait for 10 ns;
t_clk <= '1'; wait for 10 ns;
end process clock;
stimulus : process is
begin
t_rst <= '1';
t_do_count <= '0';
t_total <= (others =>'0');
wait for 15 ns;
t_rst <= '0';
wait for 10 ns;
t_do_count <= '1';
wait for 10 ns;
t_do_count <= '0';
wait for 10 ns;
t_do_count <= '1';
wait for 10 ns;
t_do_count <= '0';
wait for 10 ns;
wait;
end process stimulus;
end architecture run_test_counter;
Update 03-Oct-2012.
BOTH the answers helped. Moving "total <= current_value" inside the process (From #simon) and removing the extra "t_total <= (others =>'0');" (From #peter-bennett) in my testbench was required. I had to do both to get rid of the X's.
It looks like your mistake is in your testbench. The signal t_total is mapped to the total output of your counter component, yet you are writing to it with the t_total <= (others => '0') assignment. If you remove this I think your problem will go away.
uut : d_counter
port map( rst => t_rst,
clk => t_clk,
do_count => t_do_count,
total => t_total );
clock : process is
begin
t_clk <= '0'; wait for 10 ns;
t_clk <= '1'; wait for 10 ns;
end process clock;
stimulus : process is
begin
t_rst <= '1';
t_do_count <= '0';
t_total <= (others =>'0'); <-- Do not assign to t_total (its an output)
Your code write multi-driven with "total". You should delete assigment in process count_up.
count_up : process(clk) is
begin
if rst='1' then
current_value <= (others=>'0');
total <= (others=>'0'); --> Remove it
elsif rising_edge(clk) then
if do_count='1' then
current_value <= current_value + to_unsigned(1,16);
end if;
end if;
end process count_up;
total <= current_value; -- Keep it