I am new to VHDL and I have an issue writing a 4-bit comparator.
When I want to compare different sets of inputs there is only one output for all of them. And I don't know how to solve this problem. I want to have only one output and need to show 0000 if A is less than B, and 1111 if A is greater than B, and 0011 if they are equal. Can anybody please help me with my problem?
Here is my code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comp_4 is
port ( A:IN STD_LOGIC_VECTOR(3 downto 0);
B:IN STD_LOGIC_VECTOR(3 downto 0);
output:OUT STD_LOGIC_VECTOR(3 downto 0)
);
end comp_4;
architecture dataflow of comp_4 is
begin
process
begin
if (A=B) then
output <= "0011";
elsif (A>B) then
output <= "1111";
else
output <= "0000";
end if;
wait;
end process;
end dataflow;
And also my test bench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Comparator_test IS
END Comparator_test;
ARCHITECTURE Ctest OF Comparator_test IS
COMPONENT comp_4 IS
port( A:IN STD_LOGIC_VECTOR(3 downto 0);
B:IN STD_LOGIC_VECTOR(3 downto 0);
output:OUT STD_LOGIC_VECTOR(3 downto 0)
);
END COMPONENT;
SIGNAL a : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL b : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL c : STD_LOGIC_VECTOR(3 downto 0);
BEGIN
uut : comp_4 PORT MAP(a, b , c);
a <= "0100" , "1111" After 10 NS;
b <= "0101" , "1100" AFTER 10 NS;
END Ctest;
And my simulation looks like this:
You need to put the inputs on the sensitivity list.
Note, wait; stops the process infinitely (only in simulation, it cannot be synthesized).
Solution 1:
Use the process' sensitivity list, and remove wait;.
architecture dataflow of comp_4 is
begin
process(A, B)
begin
if (A = B) then
output <= "0011";
elsif (A > B) then
output <= "1111";
else
output <= "0000";
end if;
end process;
end dataflow;
Solution 2:
Use the sensitivity list of wait.
architecture dataflow of comp_4 is
begin
process
begin
if (A = B) then
output <= "0011";
elsif (A > B) then
output <= "1111";
else
output <= "0000";
end if;
wait on A, B;
end process;
end dataflow;
Related
Hi pleople this is my code, and the only error is Error (10028): Can't resolve multiple constant drivers for net "D[22]" at bonus2.vhd(26). I<m new at this and I don't understant this error.
Here is my code
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bonus2 is
port (
B,C : in unsigned(15 downto 0);
clear, clk : in std_logic;
Q : out unsigned(31 downto 0)
);
end entity bonus2;
architecture arch_bonus2 of bonus2 is
signal mult : unsigned(31 downto 0); --signal d'addition
signal D: unsigned(31 downto 0); --signal d'addition
begin
mult <= B * C;
process(clear)
begin
if clear = '1' then
D <= x"00000000";
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
D <= mult + D;
end if;
end process;
Q <= D;
end architecture arch_bonus2;
Your code shows that you might be unfamiliar with some concepts of hardware design, so I suggest you catch up on combinational/sequential logic and how to describe them with VHDL. Also, a good rule of thumb is that you should be able to draw some parts of your design, and if you do you'll see that the D wire is driven by multiple nets.
What I believe you want to do, based on your code, is to be able to reset/initialize your output register. However, the way you have coded it suggests you want an asynchronous reset.
Please check here to know more about synch vs asynch logic and then I suggest you to explore further to understand the implications.
Here is a modified version of your code with an asynchronous reset, because it seems what you want.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bonus2 is
port (
B,C : in unsigned(15 downto 0);
clear, clk : in std_logic;
Q : out unsigned(31 downto 0)
);
end entity bonus2;
architecture arch_bonus2 of bonus2 is
signal mult : unsigned(31 downto 0); --signal d'addition
signal D: unsigned(31 downto 0); --signal d'addition
begin
mult <= B * C;
process(clk,clear)
if clear == '1' then
D <= x"00000000";
elsif rising_edge(clk) then
D <= mult + D;
end if;
end process;
Q <= D;
end architecture arch_bonus2;
I'm doing a BCD counter that can count up/down depending on the input signals. This is the requirement:
This is my VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- main
entity BCDcounter is
port(
D_in: in std_logic_vector(3 downto 0);
enable_in, load_in, up_in, clr_in, clk_50hz: in std_logic;
C_out: out std_logic;
LED0: out std_logic_vector(0 to 6)
);
end BCDcounter;
architecture Behavioral of BCDcounter is
signal Q_temp: std_logic_vector(3 downto 0);
signal clk_1hz: std_logic;
component Clock_Divider is
port ( clk,reset: in std_logic;
clock_out: out std_logic);
end component;
component BCD_counter is
port(
D: in std_logic_vector(3 downto 0);
enable, load, up, clr, clk: in std_logic;
Q: std_logic_vector(3 downto 0);
Cout: out std_logic
);
end component;
component led IS
PORT ( input : IN STD_LOGIC_VECTOR(3 downto 0);
output : OUT STD_LOGIC_VECTOR(6 downto 0));
end component;
begin
stage0: Clock_Divider port map(clk_50hz, clr_in, clk_1hz);
stage1: BCD_counter port map(D_in, enable_in, load_in, up_in, clr_in, clk_1hz, Q_temp, C_out);
stage2: led port map(Q_temp, LED0);
end Behavioral;
-- 1-digit BCD counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCD_counter is
port(
D: in std_logic_vector(3 downto 0);
enable, load, up, clr, clk: in std_logic;
Q: std_logic_vector(3 downto 0);
Cout: out std_logic
);
end BCD_counter;
architecture bhv of BCDcounter is
signal temp: std_logic_vector(3 downto 0);
begin
process(enable, load, up, clr, clk)
begin
if clr = '0' then
temp <= "0000";
elsif enable = '0' then
temp <= "0000";
elsif load = '1' then -- load = 1, enable = 1
temp <= D;
elsif(rising_edge(clk)) then -- load = 0, enable = 1
if up = '1' then -- count up
if temp = "1001" then
temp <= "0000";
Cout <= '1';
else
temp <= temp + 1;
end if;
else -- count down
if temp = "0000" then
temp <= "1001";
Cout <= '1';
else
temp <= temp - 1;
end if;
end if;
end if;
end process;
Q <= temp;
end bhv;
-- Clock Divider from 50MHz to 1Hz
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity Clock_Divider is
port ( clk,reset: in std_logic;
clock_out: out std_logic);
end Clock_Divider;
architecture behavioral of Clock_Divider is
signal count: integer:=1;
signal tmp : std_logic := '0';
begin
process(clk,reset)
begin
if(reset='1') then
count <= 1;
tmp <= '0';
elsif(clk'event and clk='1') then
count <= count+1;
if (count = 25000000) then
tmp <= NOT tmp;
count <= 1;
end if;
end if;
clock_out <= tmp;
end process;
end behavioral;
-- LED 7 segments
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY led IS
PORT ( input : IN STD_LOGIC_VECTOR(3 downto 0);
output : OUT STD_LOGIC_VECTOR(6 downto 0));
END led;
ARCHITECTURE behave OF led IS
BEGIN
PROCESS(input)
BEGIN
CASE input IS -- abcdefg
WHEN "0000" => output <= "0000001";
WHEN "0001" => output <= "1001111";
WHEN "0010" => output <= "0010010";
WHEN "0011" => output <= "0000110";
WHEN "0100" => output <= "1001100";
WHEN "0101" => output <= "0100100";
WHEN "0110" => output <= "0100000";
WHEN "0111" => output <= "0001111";
WHEN "1000" => output <= "0000000";
WHEN "1001" => output <= "0000100";
WHEN OTHERS => output <= "1111111";-- ALL OFF
END CASE;
END PROCESS;
END behave;
When compiling, I meet the error like this although I have already declared them above. Can anyone show me what problem with my code and how to fix this error? Thank you so much.
Your entity is called BCD_counter
entity BCD_counter is
but you have created the architecture for BCDCounter
architecture bhv of BCDcounter is
And it is quite correct, BCD_Counter has no object called clr or any of the other objects it lists.
Be careful when naming entities. I also recommend putting one entity/architecture pair per file, with the prefered method to name the file the same as the entity.
I have an array of arrays defined as the input to my entity. I used a package to define the array of arrays. In the test bench, I included that package and declared the component in the architecture but there is an error saying "formal port x does not exist in entity average. Please compare the definition of block average to its component declaration and its instantion to detect the mismatch."
Attaching the declarations below. Please help.
-- the code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package vpkg is
type m_array is array(1 downto 0, 1 downto 0) of std_logic_vector(7 downto 0);
end package;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vpkg.all;
entity average is
Port (x : in m_array;
clk : in std_logic;
y : out std_logic_vector(7 downto 0)
);
end average;
architecture avg_arch of average is
signal sum : std_logic_vector(8 downto 0) := (others => '0');
begin
process(x):
for I in 0 to 1 loop
for J in 0 to 1 loop
sum <= sum + ('0' + x(I,J));
end loop;
end loop;
end process;
y <= std_logic_vector(to_signed(to_integer(signed(sum) / 4),8));
end avg_arch;
--the test bench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vpkg.all;
entity tb_average is
-- Port ( );
end tb_average;
architecture tb_average_arch of tb_average is
component average
Port (x : in m_array;
clk : in std_logic;
y : out std_logic_vector(7 downto 0)
);
end component;
signal x : m_array;
signal clk : std_logic := '0';
signal y : std_logic_vector(7 downto 0);
begin
average_1 : average Port Map (x => x,clk => clk,y=>y);
input_proc : process
begin
wait for 100ns;
x(0,0) <= "00001001";
x(0,1) <= "00000110";
x(1,0) <= "00000011";
x(1,1) <= "00000001";
wait;
end process;
clk_proc : process
begin
wait for 100ns;
loop
clk <= '1';
wait for 10ns;
clk <= '0';
wait for 10ns;
end loop;
end process;
end tb_average_arch;
I am rather new (3 weeks) to VHDL, and I am having a problem in my latest assignment, which involves implementing overflow checking in a simple 4-bit adder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity add_sub_4bit is
Port ( a : in STD_LOGIC_VECTOR(3 downto 0);
b : inout STD_LOGIC_VECTOR(3 downto 0);
sel: in STD_LOGIC );
--sum : inout STD_LOGIC_VECTOR(3 downto 0)
end add_sub_4bit;
architecture Behavioral of add_sub_4bit is
signal localflow : STD_LOGIC;
signal localsum : STD_LOGIC_VECTOR (3 downto 0);
begin
localsum <= a + b when sel = '1'
else
a - b;
process(a,b,localsum) begin
if a(3) = '0' AND b(3) = '0' AND localsum(3) = '1' then
localflow <= '1';
elsif a(3) = '1' AND b(3) = '1' AND localsum(3) = '0' then
localflow <='1';
else
localflow <='0';
end if;
end process;
end Behavioral;
Now, the test cases are as such:
A=5, B=-3, giving 0 to sel adds them, 1 subtracts.
A=6, B=2, working much the same.
Now, given that the numbers are signed, of course, they are two's complement numbers, so is the result. However, I can only detect overflow in a case of adding 6 (0110) and 2 (0010), giving out -8 (1000), which is obviously an overflow case in 4-bit. But, when doing 5 -(-3), the result is much the same, 1000, but since I have given numbers of two different signs, I cannot detect overflow using my method.
My teacher has suggested that we change the sign of B depending on the value of sel - I tried something like making b <= b+"1000" based on that but that didn't help, and I don't know of other ways, being very new to the language. What can I do to get a proper program? Thank you.
Firstly:
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Don't do that. Especially if you want the numbers to be signed. Normal to use is:
use IEEE.numeric_std.all;
After that, you should cast the std_logic_vector to the wanted data type, e.g. 'signed', for the correct arithmetic.
Secondly, don't use inout. VHDL is not so good with bidirectional assignments. Either use in or out.
So combining the above, you could do (n.b. not the best code):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity add_sub_4bit is
Port (
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
sel: in STD_LOGIC;
sum : out STD_LOGIC_VECTOR(3 downto 0);
overflow : out std_logic
);
end add_sub_4bit;
architecture Behavioral of add_sub_4bit is
signal localflow : STD_LOGIC;
signal locala, localb, localsum : signed(4 downto 0); -- one bit more then input
signal sumout : std_logic_vector(4 downto 0);
begin
locala <= resize(signed(a), 5);
localb <= resize(signed(b), 5);
localsum <= locala + localb when sel = '1' else locala - localb;
-- overflow occurs when bit 3 is not equal to the sign bit(4)
localflow <= '1' when localsum(3) /= localsum(4) else '0';
-- convert outputs
sumout <= std_logic_vector(localsum);
--outputs
sum <= sumout(4)&sumout(2 downto 0);
overflow <= localflow;
end Behavioral;
You can test this using a testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity add_sub_4bit_tb is
end add_sub_4bit_tb;
architecture Behavioral of add_sub_4bit_tb is
signal sel : std_logic_vector(0 downto 0);
signal a, b, sum : std_logic_vector(3 downto 0);
begin
uut: entity work.add_sub_4bit
port map (a, b, sel(0), sum);
test: process
begin
for sel_o in 0 to 1 loop
sel <= std_logic_vector(to_signed(sel_o, 1));
for a_o in -8 to 7 loop
a <= std_logic_vector(to_signed(a_o, 4));
for b_o in -8 to 7 loop
b <= std_logic_vector(to_signed(b_o, 4));
wait for 1 ns;
end loop;
end loop;
end loop;
wait;
end process;
end Behavioral;
This code should be (and is) very simple, and I don't know what I am doing wrong.
Here is description of what it should do:
It should display a number on one 7-segment display. That number should be increased by one every time someone presses the push button. There is also reset button which sets the number to 0. That's it. Here is VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PWM is
Port ( cp_in : in STD_LOGIC;
inc : in STD_LOGIC;
rst: in std_logic;
AN : out STD_LOGIC_VECTOR (3 downto 0);
segments : out STD_LOGIC_VECTOR (6 downto 0));
end PWM;
architecture Behavioral of PWM is
signal cp: std_logic;
signal CurrentPWMState: integer range 0 to 10;
signal inco: std_logic;
signal temp: std_logic_vector (3 downto 0);
begin
--cp = 100 Hz
counter: entity djelitelj generic map (CountTo => 250000) port map (cp_in, cp);
debounce: entity debounce port map (inc, cp, inco);
temp <= conv_std_logic_vector(CurrentPWMState, 4);
ss: entity decoder7seg port map (temp, segments);
process (inco, rst)
begin
if inco = '1' then
CurrentPWMState <= CurrentPWMState + 1;
elsif rst='1' then
CurrentPWMState <= 0;
end if;
end process;
AN <= "1110";
end Behavioral;
Entity djelitelj (the counter used to divide 50MHz clock):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PWM is
Port ( cp_in : in STD_LOGIC;
inc : in STD_LOGIC;
rst: in std_logic;
AN : out STD_LOGIC_VECTOR (3 downto 0);
segments : out STD_LOGIC_VECTOR (6 downto 0));
end PWM;
architecture Behavioral of PWM is
signal cp: std_logic;
signal CurrentPWMState: integer range 0 to 10;
signal inco: std_logic;
signal temp: std_logic_vector (3 downto 0);
begin
--cp = 100 Hz
counter: entity djelitelj generic map (CountTo => 250000) port map (cp_in, cp);
debounce: entity debounce port map (inc, cp, inco);
temp <= conv_std_logic_vector(CurrentPWMState, 4);
ss: entity decoder7seg port map (temp, segments);
process (inco, rst)
begin
if inco = '1' then
CurrentPWMState <= CurrentPWMState + 1;
elsif rst='1' then
CurrentPWMState <= 0;
end if;
end process;
AN <= "1110";
end Behavioral;
Debouncing entity:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY debounce IS
PORT(pb, clock_100Hz : IN STD_LOGIC;
pb_debounced : OUT STD_LOGIC);
END debounce;
ARCHITECTURE a OF debounce IS
SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
-- Debounce Button: Filters out mechanical switch bounce for around 40Ms.
-- Debounce clock should be approximately 10ms
process
begin
wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1');
SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1);
SHIFT_PB(3) <= NOT PB;
If SHIFT_PB(3 Downto 0)="0000" THEN
PB_DEBOUNCED <= '1';
ELSE
PB_DEBOUNCED <= '0';
End if;
end process;
end a;
And here is BCD to 7-segment decoder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder7seg is
port (
bcd: in std_logic_vector (3 downto 0);
segm: out std_logic_vector (6 downto 0));
end decoder7seg;
architecture Behavioral of decoder7seg is
begin
with bcd select
segm<= "0000001" when "0000", -- 0
"1001111" when "0001", -- 1
"0010010" when "0010", -- 2
"0000110" when "0011", -- 3
"1001100" when "0100", -- 4
"0100100" when "0101", -- 5
"0100000" when "0110", -- 6
"0001111" when "0111", -- 7
"0000000" when "1000", -- 8
"0000100" when "1001", -- 9
"1111110" when others; -- just - character
end Behavioral;
Does anyone see where I made my mistake(s) ?
I've tried that design on Spartan-3 Started board and it isn't working ... Every time I press the push button, I get crazy (random) values. The reset button is working properly.
Thanks !!!!
I guess the problem is here:
process (inco, rst)
begin
if inco = '1' then
CurrentPWMState <= CurrentPWMState + 1;
elsif rst='1' then
CurrentPWMState <= 0;
end if;
end process;
When rst='1' you will reset CurrentPWMState. But when inco='1' the you endlessly add 1 to CurrentPWMState. That's something like an asynchronous feedback loop through a latch. You should do something edge sensitive here. Probably you should capture inco using your clock signal, detect a 0->1 change and then add 1.
Agree with the previous answer.
A code like this should do the trick:
process (inco, ps, rst)
begin
if rst='1' then
CurrentPWMState <= '0';
prev_inco <= inco; -- This signal captures the previous value of inco
elsif ps'event and ps='1' then
if inco='1' and prev_inco='0' then -- Capture the flank rising.
CurrentPWMState <= CurrentPWMState + 1;
end if;
prev_inco <= inco;
end if;
end process;
I recognize I haven't tried the code (just coded in here) but I think it's ok.