I'm learning about cache, and I learned that for an address in a specific memory, part of it is used as an index and the rest is used as a tag bit.
But in the picture below, how is the memory address 00001 in the picture on the left connected to the 32-bit address in the picture on the right?
Does the 5-bit address in the picture on the left and the 32-bit address on the right mean the same thing?
For the picture on the left, the 5-bit address would decompose like this:
+-----------------------+
| Tag | Index | Offset |
+-----------------------+
2 3 0 # bits in each field
So, the tag has 2 bits, the index has 3 bits, and the block size (which determines the number of bits in the byte offset) is either 0 or simply not shown.
Related
To start off, the first cache has 16 one-word blocks. As an example I will use 0x03 memory reference. The index has 4 bits (0011). It is clear that the bits equal 3mod16 (0011 = 0x03 = 3). However I am getting confused using this mod equation to determine block location in a cache with offset bits.
The second cache has a total size of eight two-word blocks. This means that there is 1 offset bit. Since there are now 8 blocks, there are only 3 index bits. As an example, I will take the same memory reference of 0x03. However now I am having trouble mapping to the block using the mod equation I used before. I try 3mod8 which is 3, however in this case, since there is an offset bit, the index bits are 001. 001 is not equal to 3 so what did I do wrong? Does mod not work when there are offset bits? I was under the impression that the mod equation would always equal the index bits.
Its all in the address. You get the address, then mask off number of bits from the end, for following reasons.
Number of words in the cacheline. If you've got 2 word cacheline (take a bit out, 4 word - 2 bts etc)
Then how many cacheline entries you have. (If is a 1024 cacheline, you takeout 10 bits. This 10 bits is your index, remaining bits are for your Tag)
Now, you also need to consider 'WAY' as well. If its a direct mapped cache, above applies. If its a 2 way set associative cache, you dont have 1024 lines, what you have a 512 blocks with each having 2 lines in them. Which means you only need 9 bits to determine the index of the block. If its 4 way, you've got 256 blocks with 4 lines in them, meaning you only need 8 bits for your index.
In a set associative cache, index are there to choose a block, once a block is chosen, use can use a policy like LRU to fill an entry in case of a cache miss. Hits are determined by comparing the tag in the selected block.
Bottom line, block location is not determined by the address, only a block is selected by the address and thereafter its Tag comparison to find the data.
I've read several topics about this theme but I could not get the answer. So my question is:
1) How is the block offset calculated?
I want to know not the formula but the concept of it. As I know it is quantity of cases which a block can store the address. For example If there is a block with 8 byte storage and has to store 2 byte addresses. Does its block offset is 2 bit?(So there is 4 cases to store the address (the diagram below might make easier to see what I am saying).
The block offset is simply calculated as log2 cache_line_size.
The reason is that all system that I know of are byte addressable. So you need enough bits to index any byte in the block. Although most systems have a word size that is larger than a single byte, they still support offsets of a single byte gradulatrity, even if that is not the common case.
So for the example you mentioned of an 8-byte block size with 2-byte word, you would still need 3 bits in order to allow accessing any byte. If you had a system that was not byte addressable then you could use just 2 bits for the block offset. But in practice all systems that I know of are byte addressable.
There is a logical address space of 8 pages, and each page is 2KB.
The physical address space has 4 frames (size of a frame equals the size of a page).
I am given a sketch where there is an arrow from page number 0 to frame 1 that indicate a mapping between page 0 to frame 1.
I need to find the physical address of the logical address 2500.
I would like to know if my solution is correct.
This is my solution:
Because a size of a page is 2KB, that means that we need 14 bits for the offset. (cause 2KB=2^14)
And there are 8 pages (0 to 7) so we need 3 bits for the page number.
So the given virtual address in binary is:
000 00100111000100 =2500
first 3 bits from left - 000 - indicates page number 0
the rest of the bits - 00100111000100 - indicates the offset 2500
page 0 ----->frame 1 (mapping in the sketch)
So my physical address will be:
0100100111000100 = 18884.
first 2 bits -indicate the frame number- 01.
rest of the bits - indicates the offset - 00100111000100.
(there are 4 frames and therefor we need 2 bits for frame number).
I ll appreciate a response.
Thanks,
Shiran
2KB = 2^1 * 2^10 = 2^11 ---> 11 Bits, Not 14
The logic address is continuous, and you can follow steps
(1) calculate 2500/(2*1024)
the quotient is 1 --> page no. of logic address
the remainder is 452 --> offset of logic address
-->same is offset of physical address
(2) find frame no. of physical address page no. (ie, 1 from above calculation) of logical address refers to. Unfortunately the mapping is not given in the question. Let's assume page 1 in logic address is mapped into frame 4 in physical address.
(3) the physical address is [frame no.]*[frame full length] + offset, i.e.,
4*(2*1024)+452 = 8644 or 0010000111000100 (binary) or 21c4(H).
Hope it helps.
Hey all i have a question and an answer, but i cant understand the second part of the answer!
Could any1 here please help me out?
Here it is:
Question;
A computer has 32-bit virtual addresses and 4-K.B pages. The program and data together fit in the lowest page (0-4095) The stack fits in the highest page. How many entries are needed in the page table if traditional (one-level) paging is used? How many page table entries are needed for two-level paging, with 10 bits in each part?
Answer;
For a one-level page table, there are 2^32 /2^12 or 1M pages needed. Thus the
page table must have 1M entries. For two-level paging, the main page table
has 1K entries, each of which points to a second page table. Only two of
these are used. Thus in total only three page table entries are needed, one in
the top-level table and one in each of the lower-level tables.
I cant understand the bolded. for example i cant understand how this 1K comes up.
Thanks for your time,
Cheers!
I think, the answer to the first part of the question is wrong because you are not using the context of the question: The program and data together fit in the lowest page (0-4095) The stack fits in the highest page. So, while the total number of page table entries is 1048576, of those you only use 2 entries, one for each of those 2 pages (entry 0 points at the code/data page and entry 1048575 points at the stack page).
For the second part of the question you're given an extremely useful hint: two-level paging, with 10 bits in each part. But first, let's go back to the above, simpler case...
In case 1 with one page table, virtual addresses:
have 32 bits (given as A computer has 32-bit virtual addresses)
their 12 least significant bits indicate a location within a page (given as A computer has ... 4-K.B pages, also as fit in the lowest page (0-4095))
The remaining 20 most significant bits obviously select an entry in the page table. The selected page table entry contains the physical address of the page.
So, the virtual addresses look like this:
most significant bits least significant bits
| 20 bits = index into the page table | 12 bits = index into the page |
Hence, the CPU uses this formula to access memory:
PhysicalAddress = PageTable[VirtualAddress / 4096] + VirtualAddress modulo 4096
Now, let's get back to case 2.
You still have the 12 LSB bits to select a byte in the page.
But What's new? It's two-level paging, with 10 bits in each part.
Those 10 bits are the lengths of page table indices, which you now have two.
With this we arrive at the following break-down for virtual addresses:
most significant bits least significant bits
| 10 bits = PT index | 10 bits = PT index | 12 bits = page index |
And the address translating formula, naturally, is:
PhysAddr = PageTable[VirtAddr / (1024*4096)][(VirtAddr / 4096) modulo 1024] + VirtAddr modulo 4096
Now, we still have the same program that occupies 2 pages.
The virtual addresses pointing at the code/data page are (in binary):
0000000000|0000000000|xxxxxxxxxxxx
And the virtual addresses pointing at the stack page are (in binary as well):
1111111111|1111111111|xxxxxxxxxxxx
From this you can see that you are using 2 different page table entries at level 1 (selected by indices 0000000000 and 1111111111) and similarly 2 different page table entries at level 2.
So, in case 2 the total is 2+2=4 page table entries needed for the program to operate.
P.S. in case you don't remember: 210 = 1024, 212 = 4096, 220 = 1048576.
In real mode segmented memory model, a segment always begins on a paragraph boundary. A paragraph is 16 bytes in size so the segment address is always divisible by 16. What is the reason/benefit of having segments on paragraph boundaries?
It's not so much a benefit as an axiom - the 8086's real mode segmentation model is designed at the hardware level such that a segment register specifies a paragraph boundary.
The segment register specified the base address of the upper 16 bits of the 8086's 20 bit address space, the lower 4 bits of that base address were in essence forced to zero.
The segmented architecture was one way to have the 8086's 16-bit register architecture be able to address a full megabyte(!) of address space (which requires 20 bits of addressing).
For a little more history, the next step that Intel took in the x86 architecture was to abstract the segment registers from directly defining the base address. That was the 286 protected mode, where the segment register held a 'selector' that instead of defining the bits for a physical base address was an index into a a set of descriptor tables that held information about the physical address, permissions for access to the physical memory, and other things.
The segment registers in modern 32-bit or larger x86 processors still do that. But with the address offsets being able to specify a full 32-bits of addressing (or 64-bits on the x64 processors) and page tables able to provide virtual memory semantics within the segment defined by a selector, the programming model essentially does away with having to manipulate segment registers at the application level. For the most part, the OS sets the segment registers up once, and nothing else needs to deal with them. So programmers generally don't even need to know they exist anymore.
The 8086 had 20 address lines. The segment was mapped to the top 16, leaving an offset of the bottom 4 lines, or 16 addresses.
The Segment register stores the address of the memory location where that segment starts. But Segment registers stores 16 bit information. This 16 bit is converted to 20 bits by appending 4 bits of 0 to the right end of the address. If a segment register contains 1000H then it is left shifted to get 10000H. Now it is 20 bits.
While converting we added 4 bits of 0 to the end of the address. So every segment in memory must begin with memory location where the last 4 bits are 0.
For ex:
If a segment starts at 10001H memory location, we cannot access it because the last 4 bits are not 0.
Any address in segment register will be appended with 4 bits in right end to convert to 20bits. So there is no way of accessing such an address.