variable must be constrained error - vhdl

Question

I am getting an error and I don't understand why.
my code :
library ieee;
use ieee.std_logic_1164.all;
use work.Func_Pack.all;
use ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.ALL;
--use ieee.numeric_std.all;
entity letters_arranger is
port (
clock, reset,start,rdy_to_get_new_letter :in std_logic; -- asuuming clock is 27 M Hz
select_input : in integer;
reg : out std_logic_vector(7 downto 0);
drive_letter : out std_logic
);
end letters_arranger ;
architecture behave of letters_arranger is
type state is (idle, set_str, send_str,endstring);
signal cur_state: state;
--signal str :string :=" "&CR;
signal str :string :=" "&CR;
signal counter :integer;
constant letters_max : integer := 47;
begin
pro:process(clock,reset)
variable data_count : integer range 0 to 10 :=0;
begin
if (reset='1') then
cur_state <= idle;
elsif rising_edge(clock) then
case cur_state is
when idle=>
drive_letter<='0';
if start = '1' then
cur_state <= set_str;
counter<=0;
elsif counter = letters_max then
cur_state <= endstring;
elsif rdy_to_get_new_letter ='1' then
cur_state <= send_str;
end if;
when set_str =>
str <= select_str(select_input);
counter<=1;-- check char pos indx start fr 0 or 1
when send_str =>
cur_state <= idle;
if counter<=str'length then
counter<=counter+1;
end if;
reg<=conv_std_logic_vector(character'pos(str(counter)),8);
drive_letter<='1';
when endstring =>
--need to do something
cur_state <= idle;
when others => null;
end case;
end if;
end process;
end behave;
and my funcpack (only the function select_str is relevant I believe ):
------------------------ Func_Pack.vhd program ------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
PACKAGE Func_Pack IS
------------Type Decalration ---------------
SUBTYPE byte IS std_logic_vector(7 downto 0);
TYPE special_message IS array(0 to 4,0 to 100) OF byte;
--------------------------------------------
FUNCTION Parity_calc ( data : std_logic_vector(7 downto 0) )RETURN std_logic ;
FUNCTION To_7Seg ( data:integer range 0 to 9)RETURN std_logic_vector;
FUNCTION select_str ( indx:integer range 0 to 9) RETURN string;
END Func_Pack;
----------------------------------------------------------------------------------------------------------------------------
PACKAGE BODY Func_Pack IS
--parity_calc--
FUNCTION Parity_calc ( data : std_logic_vector(7 downto 0) )RETURN std_logic IS
VARIABLE temp : std_logic ;
BEGIN
temp := data(0) xor data(1) xor data(2) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7);
return (temp);
end parity_calc;
----------------------------------------------------------------------------- ------------
------------------ To 7eg Convert function ---------------------------------------------
FUNCTION To_7Seg ( data:integer range 0 to 9)RETURN std_logic_vector IS
VARIABLE temp:std_logic_vector (6 downto 0):=(others=>'1');
BEGIN
CASE data IS
WHEN 0 => temp :="1000000"; -- 40h
WHEN 1 => temp :="1111001"; -- 79h
WHEN 2 => temp :="0100100"; -- 24h
WHEN 3 => temp :="0110000"; -- 30h
WHEN 4 => temp :="0011001"; -- 19h
WHEN 5 => temp :="0010010"; -- 12h
WHEN 6 => temp :="0000010"; -- 02h
WHEN 7 => temp :="1111000"; -- 78h
WHEN 8 => temp :="0000000"; -- 00h
WHEN 9 => temp :="0010000"; -- 10h
WHEN OTHERS => NULL;
END CASE;
RETURN (temp);
END To_7Seg;
FUNCTION select_str ( indx:integer range 0 to 9) RETURN string IS
VARIABLE temp:string;
BEGIN
CASE indx IS
WHEN 0 => temp :=" "&CR;
WHEN 1 => temp :="V18 "&CR;
WHEN 2 => temp :="w300 "&CR;
WHEN 3 => temp :="SPlease Choose 1 Branch line Out Of 3 Possible"&CR;
WHEN 4 => temp :="SYou chose Branch Number 1 "&CR;
WHEN 5 => temp :="SYou chose Branch Number 2 "&CR;
WHEN 6 => temp :="SYou chose Branch Number 3 "&CR;
WHEN OTHERS => temp:=" "&CR;
END CASE;
RETURN (temp);
END select_str;
-----------------------------------------------------------------------------------
--"V18"
--"W300"
--
--"SPlease Choose 1 Branch line Out Of 3 Possible" -- 46 .
--"SYou Choosed Branch Number 1"
--"SYou Choosed Branch Number 2"
--"SYou Choosed Branch Number 3" --29
--"SConnecttinngg" -- 14
--"SI Am Sorry I Couldn't Find the Branch , you tried to Reach" --59
--13 -- =D in hex == <cr> . must be sent in the end of each line
--
--type message_preset is record
-- speed: is array(0 to 2) of byte ;
-- volume: is array(0 to 3) of byte;
-- cr : is integer range 0 to 255;
--end record;
--signal message_set : message_preset := (,,);
------------------------------------------------------------------------- ---------
END Func_Pack;
when running the first code as top-level entity i get this error :
VHDL error at letters_arranger.vhd(21) variable must be constrained .
line 21 is this line
signal str :string :=" "&CR;

Answer 1

In VHDL (and globally in hardware description) you need to constrain all of your signals. Otherwise, the synthesizer can't allocate the needed resources.
That's why you should write the range of your string :
signal str :string(1 to 47) :=" "&CR;
(If I didn't fail in counting the spaces)

Answer 2

Currently all signals and variables must be explicitly sized. However, constants do not have this same restriction, so the clever work around is:
constant BL_STR :string :=" "&LF;
signal str :string(1 to BL_STR'length) := BL_STR ;
Note I changed your CR to LF. With VHDL-2008, LF is recognized as a newline for what ever operating system you are running on.