I found on https://github.com/Xilinx/XilinxBoardStore/blob/2020.1.1/boards/Xilinx/au50/production/1.0/part0_pins.xml
two pin names I dont understand. What are purpose of
<pin index="9" name ="FPGA_TXD_MSP" iostandard="LVCMOS18" loc="BB25"/>
<pin index="10" name ="FPGA_RXD_MSP" iostandard="LVCMOS18" loc="BB26"/>
in line 29?
Best'
I have found some information about the pin on the alveo product guide, section Maintenance Connector Interface, which I quote:
The Alveo U50 accelerator card provides access to the FPGA through the
JTAG interface using a debug and maintenance board (DMB) connected to
the 30-pin maintenance connector. The connector pinout supports three
UART debug interfaces: PMBus, FPGA JTAG, and satellite controller
JTAG.
(From here you can dive deeper into the UG1377)
By looking at another u50 alveo PG we can find more info about the satellite controller (page 5).
A TI MSP432 satellite controller resides on the U50/U50 LV card to
control and monitor voltages, currents and temperatures
By looking at the picture, , it seems that the PINs you are searching for are UART pins (TX,RX) to communicate to the TI satellite controller from directly the FPGA.
Related
I want to build my own SOC based on the rocket chip without the use a ROCC(arm coprocessor). I checked this useful question: rocket chip on non zynq FPGA
I looked for some detailed documentation but I only found few slides describing the configurations without an actual tutorial.
Thus, I have three questions concerning the image below:
I managed to generate the overall verilog for the tinyConfig, but is it possible to generate only the Rocket Chip, HostIO/AXI Convertor and MemIO/AXIHP Convertor ? if yes how ?
Can a debug interface be added by the rocket Chip generator ?
Where can I change the RAM used in rocket chaip by a RAM of a specific FPGA vendor ?
The verilog generated by rocket-chip can be used in FPGA. You just need to replace the behav_srams.v with the RAM generated in vivado.
In system/Config.scala, You can add class WithJtagDTMSystem to your config to generate debug interface.
I'm busy writing a driver for a UART. The, struct uart_port has a field uartclk see this link. According to a slide set I found from free-electrons, this is among the most important fields to initialize. Yet, the Xilinx AXI UART Lite, which I'm writing a driver for, doesn't initialize this member see this link to see.
I'm wondering about the importance of this field. What is this in relation to a UART? Why is it important? What role does it play in the serial core?
Thanks
P.S. I know there's a driver existing. However, this driver assumes the UART Lite is to be used in an embedded environment. In the application I'm writing to, this is not the case.
The UART like any other IP in the system has to have functional and interface clocks. In some IPs it might be same clock, in some it might be more interface or functional clocks. The uartclk field reflects the actual frequency on the input to baudrate generator (don't be confused by the frequency of functional clock which most of the time is constant). When user calls termios to set a desired baudrate the UART driver for actual hardware recalculates uartclk, if needed, and bottom layer, if used, configures the registers. That's how 8250 works. In other cases it might be left unused, if, for example, serial hw driver does everything on its own.
In QSYS I have an ADC, PLL and an Avalon-MM Read Master to access the internal ADC of the Altera Max10. The control and user interface of the Read Master are exported.
Now I struggle to setup the control interface to access the ADC channels. Mainly following signals:
control_fixed_location
control_read_base
control_read_length
The interface description is:
The block diagram for the Read Master is:
Questions:
- How do I need to set the control signals to access the ADC channel x?
- Where can I find the base address for the ADC implemented in QSYS?
Attached is the quartus archive. Maybe someone can give me an example to simulate this interface in ModelSim.
Thanks in advance!
I have an answer to your second question. I am struggling myself with the first question.
Where can I find the base address for the ADC implemented in QSYS?
I know two methods to find the base and end address of a component.
One is to open the System Contents view (standard) and scroll to the right side .
I am not permited to embed images yet.
There you see a row named Base and End. Here you can find the addresses.
The second method is to open the Address Map. Should be located in the same column as System Contents, or you can select View in the top left corner and select it there.
Have a look. You should be able to find it yourself with this information.
What i use when i am searching for examples or prebuild designs is the altera website. Here a link for you https://cloud.altera.com/devstore/platform/
Probably you like this one: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max-10/ug_m10_adc.pdf
The configuration is complete in QSYS? Like selecting channels and Sequencer in your ADC Block. Selecting the right input clocks and the right frequencies?
You wrote:
In QSYS I have an ADC, PLL and an Avalon-MM Read Master to access the internal ADC of the Altera Max10. The control and user interface of the Read Master are exported.
Have you created a clock for your PLL? When i want to simulate a clock signal for a QSYS system i export the clock signals and define the wanted clock in an additional file.
When you go one step further and include a nios2 processor i recommend to have a look at the altera_modular_adc.c file.
*edit
If you haven't assigned any base addresses there is a function in QSYS which does the job for you.
In System (Same column as File) -> Assign Base Addresses
I've looked over the info on BSCANE2 in http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf (pg 169 7 Series FPGA Configuration Guide) and I can't quite figure out how to use it based on that descriptions.
I want to be able to use the JTAG port on the KC705 board to shift in some configuration data for our design. I think (based on the description there in the user guide linked above) that the BSCANE2 is what I need to do that... but I really don't understand why all of the pins of the BSCANE2 component seem to have the wrong direction (TDO is an input while all of the other JTAG control sigs like TCK, RESET, TDI are outputs). Initially I had thought that there was an implicit connection from the signals of the JTAG port of the FPGA to the instantiated BSCANE2 component, but that doesn't appear to be the case based on the port directions. I suspect I'm missing some information somewhere and while I have read the docs it's still not clear to me how to actually use the BSCANE2 to do what I'm trying to do.
Any example usage of a BSCANE2 component would be appreciated.
NOTE: the description of the BSCANE2 in the user guide linked above says:
The BSCANE2 primitive allows access between the internal FPGA logic and the JTAG Boundary Scan logic controller. This allows for communication between the internal running design and the dedicated JTAG pins of the FPGA
This sounds exactly like what I need.
Xilinx offers a 8 bit CPU called PicoBlaze that uses a JTAGLoader module to reconfigure the PicoBlaze's instruction ROM at runtime. The JTAGLoader is provided in VHDL for Spartans and Series-7 devices.
But I think JTAG is not a good protocol for data transfer. Especially the JTAG software API is a mess.
What about UART? Most boards have a USB-UART bridge like CP2103 that supports up to 1 MBoud.
I'm attempting to use the ALS Pmod with the Basys2 board in VHDL.
How would I go about doing so?
With a 3-wire SPI™ communication interface. The Texas Instruments ADC081S021 Single Channel, 50 to 200 ksps, 8-Bit A/D Converter (PDF data sheet) is intended to be polled. Note from the TI datasheet you don't need a full SPI slave interface, it's read only, a simple port. From the schematic for the PMOD-ALS it appears it operates in continuous tracking mode.