Error (10476): VHDL error at PEnc83.vhd(42): type of identifier "sy" does not agree with its usage as "std_ulogic" type - vhdl

Question

I'm new to VHDL and I don't understand what is giving me the error:
Error (10476): VHDL error at PEnc83.vhd(42): type of identifier "sy" does not agree with its usage as "std_ulogic" type
This error also applies for "sz".
Here is my code:
library ieee;
use ieee.std_logic_1164.all;
entity PEnc83 is
port(I: in STD_LOGIC_VECTOR(7 downto 0);
O: out STD_LOGIC_VECTOR(2 downto 0);
V: out STD_LOGIC_VECTOR);
end PEnc83;
architecture arq_penc83 of PEnc83 is
component PEnc421
port(
a: in STD_LOGIC_VECTOR(3 downto 0);
b: out STD_LOGIC_VECTOR(1 downto 0);
v: out std_logic_vector);
end component;
component MUX2
port(A, B: in STD_LOGIC_VECTOR(1 downto 0);
sel: in std_logic;
O: out STD_LOGIC_VECTOR(1 downto 0));
end component;
SIGNAL sa, sx, sb : std_logic_vector(1 downto 0);
SIGNAL sy, sz : std_logic_vector;
Begin
UPEnc1: PEnc421 port map (
a => I,
b => sa,
v => sy);
UPEnc2: PEnc421 port map (
a => I,
b => sx,
v => sz);
UPEnc3: PEnc421 port map (
a(0) => sy,
a(1) => sz,
a(2) => '0',
a(3) => '0',
b => sb,
v => V);
UMUX2: MUX2 port map(
A => sa,
B => sx,
sel => sb(2),
O => O);
O(2) <= sb(2);
end arq_penc83;
Since sy and sz are signals it should work like the other ones. But for some reason it just isn't, maybe is it because they are only 1 vector, but they are supposed to be only one vector that connects to PEnc3.

Answer 1

Change line 42 to "a(0) => sy(0)", change line 43 in the same way. Then the compiler will probably accept your code.

Answer 2

You have multiple errors in your source:
If you mean a single bit, use std_logic instead of std_logic_vector. I interpreted all places without constraints (( .. downto .. )) as such.
If you want to connect only parts of a vector, you need to specify this. This is specifically necessary where you assign vectors of different widths.
Do not use indexes outside the constraints.
Presumably you became confused when you "wired" the multiplexer.
This is a corrected source, which does not produce syntax errors. However, it can have logical errors, because I don't know the logic you try to implement.
library ieee;
use ieee.std_logic_1164.all;
entity PEnc83 is
port(I: in STD_LOGIC_VECTOR(7 downto 0);
O: out STD_LOGIC_VECTOR(2 downto 0);
V: out STD_LOGIC);
end PEnc83;
architecture arq_penc83 of PEnc83 is
component PEnc421
port(
a: in STD_LOGIC_VECTOR(3 downto 0);
b: out STD_LOGIC_VECTOR(1 downto 0);
v: out std_logic);
end component;
component MUX2
port(A, B: in STD_LOGIC_VECTOR(1 downto 0);
sel: in std_logic;
O: out STD_LOGIC_VECTOR(1 downto 0));
end component;
SIGNAL sa, sx, sb : std_logic_vector(1 downto 0);
SIGNAL sc, sy, sz : std_logic;
Begin
UPEnc1: PEnc421 port map (
a => I(7 downto 4),
b => sa,
v => sy);
UPEnc2: PEnc421 port map (
a => I(3 downto 0),
b => sx,
v => sz);
UPEnc3: PEnc421 port map (
a(0) => sy,
a(1) => sz,
a(2) => '0',
a(3) => '0',
b => sb,
v => V);
UMUX2: MUX2 port map(
A => sa,
B => sx,
sel => sb(0),
O => O(1 downto 0));
O(2) <= sc;
end arq_penc83;