Errors compiling Linux Kernel mode program - linux-kernel

I wish to access some registers of my ARM Cortex-A8 board which are by default in a non-accessible state. Ubuntu 9.10 runs on this board. So, to access them I have to in-turn change 1 other register settings (Allow-access-register) first. To change this Allow-access-register, I found out that I must do it only in Kernel mode and not in the user mode.
So, I referred how to program in Kernel mode and I got to this wonderful tutorial. I wrote this small hello world program and a make file. Note that I'm still running this program on my x86 Desktop (Ubutnu 10.04) and not YET on my ARM processor. Not until I get a hang over Kernel level programming.
I get these errors. Whats going wrong here?
Help!
Errors I get on my i.MX515 board
ubuntu#ubuntu-desktop:~/Documents/Kernel_Programming$ make
make -C /lib/modules/2.6.31-203-gee1fdae/build M=/home/ubuntu/Documents/Kernel_Programming modules
make[1]: Entering directory `/usr/src/linux'
make[1]: *** No rule to make target `modules'. Stop.
make[1]: Leaving directory `/usr/src/linux'
make: *** [all] Error 2
Errors I get
ubuntu#ubuntu-desktop:~/Documents$ make
make -C /lib/modules/2.6.32-23-generic/build M=/home/ubuntu/Documents modules
make[1]: Entering directory `/usr/src/linux-headers-2.6.32-23-generic'
make[2]: *** No rule to make target `/home/ubuntu/Documents/hello-1.c',
needed by `/home/ubuntu/Documents/hello-1.o'. Stop.
make[1]: *** [_module_/home/ubuntu/Documents] Error 2
make[1]: Leaving directory `/usr/src/linux-headers-2.6.32-23-generic'
make: *** [all] Error 2
Program
#include <linux/module.h>
#include <linux/kernel.h>
int init_module(void)
{
printk(KERN_INFO "\nHello World! I'm programming in Kernel Mode\n");
return 0;
}
void cleanup_module(void)
{
printk(KERN_INFO "\nBye Bye blue bird\n");
}
makefile
obj-m +=hello-1.o
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean

I don't know if it's just the formatting of your post or not, but the kernel build scripts are looking for "Makefile" and you have "makefile" (difference in case). Could that really be the problem? Plus, is your username "ubuntu"?

There is a typo in your make command like:
It should be:
make -C /lib/modules/2.6.32-23-generic/build M=/home/ubuntu/Documents modules
not
make -C /lb/modules/2.6.32-23-generic/build M=/home/ubuntu/Documents modules

Related

“cc: command not found” when running make for libgcrypt on windows 10

G'day all. Just to preface this, I'm not an experienced programmer, so I might not use the correct jargon.
I'm in the process of installing GnuPG 2.2.19 on a Windows 10 machine (build no. 18363.628). I have installed MinGW (version 2013072300 according to mingw-get), as well as npth 1.6 and libgpg-error 1.37. I'm now attempting to install libgcrypt 1.8.5. Running ./autogen.sh --build-w32 works, but running make fails with the following output (I am using msys.bat as my shell):
$ make
make all-recursive
make[1]: Entering directory '/c/Users/USER/Downloads/libgcrypt-1.8.5.tar/libgcrypt-1.8.5/libgcrypt-1.8.5'
Making all in compat
make[2]: Entering directory '/c/Users/USER/Downloads/libgcrypt-1.8.5.tar/libgcrypt-1.8.5/libgcrypt-1.8.5/compat'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/c/Users/USER/Downloads/libgcrypt-1.8.5.tar/libgcrypt-1.8.5/libgcrypt-1.8.5/compat'
Making all in mpi
make[2]: Entering directory '/c/Users/USER/Downloads/libgcrypt-1.8.5.tar/libgcrypt-1.8.5/libgcrypt-1.8.5/mpi'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/c/Users/USER/Downloads/libgcrypt-1.8.5.tar/libgcrypt-1.8.5/libgcrypt-1.8.5/mpi'
Making all in cipher
make[2]: Entering directory '/c/Users/USER/Downloads/libgcrypt-1.8.5.tar/libgcrypt-1.8.5/libgcrypt-1.8.5/cipher'
cc -o gost-s-box ./gost-s-box.c
make[2]: cc: Command not found
make[2]: *** [gost-s-box] Error 127
make[2]: Leaving directory '/c/Users/USER/Downloads/libgcrypt-1.8.5.tar/libgcrypt-1.8.5/libgcrypt-1.8.5/cipher'
make[1]: *** [all-recursive] Error 1
make[1]: Leaving directory '/c/Users/USER/Downloads/libgcrypt-1.8.5.tar/libgcrypt-1.8.5/libgcrypt-1.8.5'
make: *** [all] Error 2
Unfortunately I accidentally closed the shell window after the first time I ran make, so this is from when I ran it a second time, hence the "Nothing to be done" stuff.
I have checked the Makefile for libgcrypt; it contains the following:
CC = mingw32-gcc
CCAS = mingw32-gcc
CCASDEPMODE = depmode=gcc3
CCASFLAGS = -g -O2
CCDEPMODE = depmode=gcc3
CC_FOR_BUILD = cc
I've checked the MinGW root folder, and gcc.exe and mingw32-gcc.exe are both present in the bin folder. I've also tried changing the first of those lines above to CC=gcc; no change.
Anyone have any suggestions as to what the problem is? Thanks in advance.
Ok, so I managed to solve it myself; after some research, I found that creating a symlink "CC.exe" to "mingw32-gcc.exe" in MinGW's bin did the trick.

Makefile object files not created

Have you ever experienced a situation when an object file was not present after successful compilation?
Running on windows using gnumake-4.2.1 and gcc-arm-none-eabi-5_4-2016q3 toolchain
I have a makefile which I am not full author of
this is interesting part
DEPFLAGS = -MT $# -MMD -MP -MF $#.d
$(OBJS_OUTPUT_FOLDER)/%.o : %.cpp
#$(CXX) -c $< -o $# $(CFLAGS) $(DEPFLAGS) $(INC_FOLDERS_INT) $(LANGUAGE_STANDARD_CPP) \
&& echo $# OK && $(CP) $# C:/build/
and this is the console output
build/bar.o OK
build/baz.o OK
build/foo.o OK
cp: can't stat 'build/foo.o': No such file or directory
make[1]: *** [Makefile:223: build/foo.o] Error 1
make[1]: *** Waiting for unfinished jobs....
Checking the file system shows that the foo.o really is not present, sometimes other files are missing as well (for example baz.o.d).
I don't really think its fault of the makefile because it gets done eventually (usually on the second to third try without cleaning).
When all of the objects are done I usually get linker error
aaa.hh:183: undefined reference to `MyNamespace::MyFun(short, short, short)'
MyFun is not in bar, baz neither in foo. The object file that should contain MyFun is present, but the size of it is total nonsense (556B), but if I manually delete it (as suggested elsewhere on SO when dealing with undefined references (as a corrupted one)) and make all again it gets done (now the size is around 1.5MB) and creates the binary.
Edit:
As the incorrect files have stable size (well, for the time being it seems so) I have added
#test `wc -c <$#` -ne 556;
to the rule(Checking file size in makefile, stopping if file is too short), this catches the wrong objects (I know specific case) and together with .DELETE_ON_ERROR: I don't have to manually delete the bad ones I find after linking the output of the console in this case is
[ CXX ] build/bar.o
make[1]: *** [Makefile:219: build/bar.o] Error 1
make[1]: *** Deleting file 'build/bar.o'
while in the other case
[ CXX ] build/foo.o
/spt/resources/sh: can't open build/foo.o: no such file
sh: 556: unknown operand
make[1]: *** [Makefile:220: build/foo.o] Error 2
so it probably is not makefile deleting it (I believe it would announce it as in the first case)
Edit2:
After setting a virtual machine (Windows 7) and making the project again (same makefile, same toolchain, same make) it goes smoothly. I guess there really is something on the host computer, maybe an antivirus or some other corporate security software...
Thanks in advance

Make going into extra directory

Im trying to make a simple hello module.
This is the c file:
#include <linux/module.h> // included for all kernel modules
#include <linux/kernel.h> // included for KERN_INFO
#include <linux/init.h> // included for __init and __exit macros
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Daniel");
MODULE_DESCRIPTION("A Simple Hello World module");
static int __init hello_init(void)
{
printk(KERN_INFO "Hello world!\n");
return 0; // Non-zero return means that the module couldn't be loaded.
}
static void __exit hello_cleanup(void)
{
printk(KERN_INFO "Cleaning up module.\n");
}
module_init(hello_init);
module_exit(hello_cleanup);
This is the makefile:
obj-m := hello.o
all:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
Ive placed them in ~/HelloModule
and when I run the make command there it gives me this error:
make -C /lib/modules/4.13.0-25-generic/build M=/home/dan/HelloModule modules
make[1]: Entering directory '/usr/src/linux-headers-4.13.0-25-generic'
scripts/Makefile.build:44: /home/dan/HelloModule/Makefile: No such file or directory
make[2]: *** No rule to make target '/home/dan/HelloModule/Makefile'. Stop.
Makefile:1550: recipe for target '_module_/home/dan/HelloModule' failed
make[1]: *** [_module_/home/dan/HelloModule] Error 2
make[1]: Leaving directory '/usr/src/linux-headers-4.13.0-25-generic'
makefile:4: recipe for target 'all' failed
make: *** [all] Error 2
For some reason on the 4th line it seems like the make script is trying to go into the directory /home/dan/HelloModule/Makefile, which isn't a directory. any ideas on why this is happening and how to fix it?
I figured it out. its not trying to access a directory its trying to access the Makefile which is case sensitive so it has to be Makefile not makefile

kernel programming: No rule to make target `−C'

I am trying to learn kernel programming but while trying to compile a simple hello world program i am getting the following error.
make −C /lib/modules/3.2.0-67-generic/build M=/home/arun/KPrograms modules
make[1]: Entering directory /home/arun/KPrograms'
make[1]: *** No rule to make target−C'. Stop.
make[1]: Leaving directory `/home/arun/KPrograms'
make: * [all] Error 2
my Makefile is
obj−m += hello−1.o
all:
make −C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
make −C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
You should replace all the −C in Makefile into -C. The dash character is incorrect.
Hi all,
You must type your code on your own. In some cases copy paste does not work. You must enter it like this:
obj-m............<enter>
all:....<enter>
<tab>make -C.............<enter>
clean:..............<enter>
<tab>make -C...........<esc> <:wq>
That will probably solve your problem.
good luck

Makefile calling other makefile with target, gives wrong target

I have a makefile with a target clean:
clean:
$(MAKE) -f <other makefile location> clean
When I call make clean in this makefile, it tells me that in the other makefile there is no rule 'clean-linux'. Specifically here is the output.
make -f /root/ovaldi-5.5.25-src/project/linux/Makefile clean
make[1]: Entering directory '/root/ovaldi-5.5.25-src'
make[2]: Entering directory '/root/ovaldi-5.5.25-src'
make[2]: *** No rule to make target 'clean-linux'. Stop.
make[2]: Leaving directory '/root/ovaldi-5.5.25-src'
make[1]: Leaving directory '/root/ovaldi-5.5.25-src'
Why is it giving it the clean-linux target and not just clean like I specified?
When you make (or $(MAKE)), by default you use whatever makefile is there. So here's what I think is happening.
You cd to some location.
You 'make -f Makefile_A clean'.
make runs with Makefile_A, and does '$(MAKE) -f Makefile_B clean'.
make[1] runs with Makefile_B, and does '$(MAKE) clean-linux'.
make[2] runs with whatever makefile is here which might be anything (I suspect it's Makefile_A) but whatever it is it has no rule for clean-linux.
The solution: rewrite your second makefile (the one that has clean-linux) so that clean-linux becomes a prerequisite of clean (if/when you're on a linux system). That way it won't run make[2].
ifeq ($(PLATFORM), LINUX)
clean: clean-linux
endif
ifeq ($(PLATFORM), SUNOS)
clean: clean-sunos
endif
clean:;
Just a guess but maybe the 'clean' target in the second makefile calls 'clean-linux'?
Can you post the clean target of the second makefile?
Edit:
In light of your posted clean target it seems you're just calling the clean-linux target incorrectly.
Beta has posted the correct way of dealing with your problem in their answer so I'm going to +1 that.

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