I want to use the Xilinx hardware module of the ICAP controller in my own design.
This module uses the following library:
library hwicap_v5_00_a;
use hwicap_v5_00_a.all;
I was looking in the directories as well as subdirectories of
Xilinx\12.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores
but I could not find the package declaration of hwicap. Anyone an idea where Xilinx "hides" this information.
Many thanks
I think you just compile all the VHDL files from
C:\Xilinx\12.3\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\hwicap_v5_00_a\hdl\vhdl
into a library called hwicap_v5_00_a - this is the way EDK works.
There's no package that I can see.
Related
There are a few modules and a package in VHDL. How will we use the package in the modules. we have already use.work.Package_name.all;
but it did not work.
And where will we store the package and the modules? Please specify an example path.
How to compile the package?
I think you should start reading a book on VHDL, or follow an on-line tutorial. Or ask your teacher/tutor.
Google also helps: vhdl packages
use work.Package_name.all;
I am trying creating a library of components that I can use in Vivado(2014.2). I have many .vhd files and I would like to add more in the future, and so I'd prefer not to have to condense them
all into a single .vhd.
I may need to use a package...
ie.
--File name: my_library_file
package my_lib_package is
--All component declarations...
end package my_lib_package;
But would all the entities and architectures also need to be in this file?
Then I could use a "use" statement to reference these elements.
ie. use my_lib.
But would the my_library_file need to be located in the same project?
I would like to be able to make this library once and be able to reference in
any project with a call.
Ideally it could be called like an IEEE library but with many vhd files being referenced.
I would prefer not to explicitly add/include these individual source files to the project, but would instead prefer to just be able to use the “use” clause with library and/or package…if possible.
Hayden - your approach to making your own package of components sounds fine. We use the same approach with a single package file of "comps". It is written as a package and has the component instance as well as the entity and architecture of each component. Look at any of the Xilinx or Altera library source files as a guide.
You can compile it into it's own library and call it just like you do with the Xilinx libraries in Vivado.
I am quite new to Vivado and VHDL and I would like some guidance on a fundamental issue.
I am guessing that I can create my own libraries and use them in my projects as i do with the default and fundamental ones
eg:
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
Now, by browsing on the net, I haven't found anything concrete as an answer, there is not any direct way to "add library" (at least in my version of Vivado).
Is there any way to build VHDL code with lets say type definitions and use them in any file you like, as it is done in C for example?
So libraries are just a method for dealing some name clashes. So Xilinx (or another vendor) can release a new entity and not have it clash with your existing objects. You can certainly do that as well, but it doesn't actually solve any problems for you.
Instead, what you are looking for is a package. Let's look at how we would use it:
Let's create another file tools.vhd
package tools is
type tribool is (true, false, maybe);
end package;
Which we could then use in our entities as:
use work.tools.all;
...
signal x : tribool := maybe;
Each file in VHDL resides inside a library (in Vivado, your designs file are in xil_defaultlib by default).
You can create/change the library a file resides in Vivado by clicking on the file, then clicking the button to the right of the Library label in the "Source File Properties" tab. You can create a library by assigning a file to a library that doesn't exist.
You will often see the library work in VHDL. Someone will correct me if I'm wrong, but work is not a library and only refers to the current library. Thus, if you have a package and an entity in the same library, you can refer the package as my_library.my_pkg or work.my_pkg.
If you want to handle libraries outside Vivado (for example large simulation models), you can precompile them, for example in Questa/Modelsim:
in vsim or .do file:
vlib path/to/MyLib
vmap MyLib path/to/MyLib
vcom -93 -work MyLib completely/other/path/to/MyLibSource.vhd
Now, Vivado has a tendency to overwrite the files in simulation folder, so don't put it there unless you want to re-compile it every time. However, Vivado should respect what is in modelsim.ini. So add to that:
MyLib = path/from/vivado/sim/to/Mylib
Now you can use MyLib as any other library:
library MyLib;
use MyLib.all;
. . .
i_MyAwesomeModel : entity MyLib.HalfAdder_Sim
I am trying to use fixed point numbers in my VHDL project, but I keep having trouble implementing the library (found here http://www.eda-stds.org/fphdl/fixed_pkg_c.vhdl). The error I receive when trying to simulate is this
<ufixed> is not declared
My question is how exactly should a library be implemented so it can be used? As of now I have added it to the project in the IEEE_PROPOSED library, but it is not working. All source code can be found here https://github.com/srohrer32/beamformer/tree/fixed_num, under the hdl folder and libraries folder.
Are you using modelsim? Are you using a project? If not... I find the best way is to first compile the library on its own. Open your modelsim.ini file and make a path to the library. Like this:
lib_test = c:/test/source/lib_test
Finally, compile your own code and make sure you use the -modelsimini switch on vcom modelsim command.
If you are using a project (which I don't like, they are not as flexible) then you can point the project to the library.
More help about modelsim compiling with commands:
http://www.tkt.cs.tut.fi/tools/public/tutorials/mentor/modelsim/getting_started/gsms.html#compiling
Not being an isim user myself, a search through the ISim User Guide implies you need to create a separate project to compile into a library, contrasting with how easy it is to target a library from the command line.
Presumably you'd also need to add the library as a resource in your project. Funny there are no complaints about that yet you have:
library ieee_proposed;
in delay_calculation.vhd, noting that a library declaration simply makes the name available. Somewhere the implementation dependent mapping for the library name to library needs to be made. This by default is in xilinxisim.ini, but I imagine your project management interface allows you to map the library into your project, and isim should know where to look for the library.
Nosing around the user guide may be worthwhile.
In Simulation Steps Overview
User Libraries
Depending upon how you launch ISim, there are different methods
available to add user libraries:
When launching Project Navigator, define the user libraries in the ISE tool. See “Working with VHDL Libraries” in ISE Help for
details.
When using ISim standalone, interactive command mode, or non-interactive mode, set the library mapping file (see Appendix A,
Library Mapping File (xilinxisim.ini) to point to your logical or
physical libraries.
When launching ISim from the PlanAhead tool, define the user libraries in that tool. See the PlanAhead User Guide (UG632) for more
information. Appendix D, Additional Resources, contains a link to the
document.
See Working with VHDL Libraries, see To Create a VHDL Library and To Add Files to a VHDL Library.
(The top level link to ISE Help).
You'd think there'd be a FAQ for those of us apostate - speed reading 'religious' tomes sucks even using Google to find them. Notice the explanations are in terms of menu pull down actions, analogous to command line entry. We're being bitten by what's available on the top menu bar. And when you do manage to add and use a library successfully you'll remember how until someone changes the menus around, and you could of course wonder about documentation lagging.
Presumably what you've tried to do is set up the library mapping for synthesis mode in the ISE GUI, which is straightforward but completely ignored by iSim since it has its own system for managing library mappings. I'm not an iSim user but after looking at the documentation and a little testing it looks like the easiest way to set up a library is from the command line:
# This creates an ieee_proposed directory with a partially compiled object.
vhpcomp --work ieee_proposed=ieee_proposed fixed_pkg_c.vhdl
# Add a mapping from the logical library to the physical path.
# *nix shown. Windows would be similar or just use a text editor.
# <logical name>=<physical path>
echo ieee_proposed=`pwd`/ieee_proposed >> path/to/your/xilinxisim.ini
Make sure the xilinxisim.ini file is visible to iSim and it should pick up the mapping to your compiled library. You should be able to keep running vhpcomp from the parent of ieee_proposed to add more files to the library. You may have to manually copy the system default version to maintain the standard library mappings.
I need to use one module, I created previously using vhdl in another module and I cant find any info on how to do this. I'm forced to use maxplus2, and the only thing I found there is that I can create include file there (will have .inc extension), but I still cant get it included in my second module. I've spent the whole morning searching for this info but found nothing.
Can anybody help me with it?
You don't.
VHDL doesn't have include files, it avoids that whole horrid disastrous unreliable mess.
VHDL uses separate compilation, and good VHDL tools (not all of them!) track all the dependencies correctly without includes or Makefiles.
So you compile your other modules into a library - maybe "my_modules" - or if you don't specify a library, just compile it, it'll go into the default library called "work".
Then in your main module you name the libraries (except "work" which is always there)
library ieee;
library my_modules;
and name the things (modules, packages) you want from them (except "work" ...)
use ieee.numeric_std.all;
use my_modules.all;
and you can now use whatever you want from these libraries. The simplest way to use a module is "direct entity instantiation" - searching this and "VHDL" will show you how.
Or you can declare a component in your main module with the same ports as your other module, and the correct module will replace the component at elaboration (VHDL term for linking). Where you would need a component is if you haven't written the library modules yet - i.e. top down design... otherwise direct entity instantiation is simpler.
For now, ignore "my_modules" and just use "work" - when you get to a big design, use libraries to organise it, e.g. keep hardware and testbenches separate.
Brian has the right answer for you. Something I'd add which is related to your question in that it's something else people use include files for:
packages are VHDL's way of sharing data-types, constants, functions and procedures.