I am stuck while solving this question,
What is the minimum number of 2 input
nand gates required to realize
I found the answer when there is no limit on the number of inputs, but cant find the answer when the constraint "2 input nand gate" is specified". Any help would be appreciated.
Well, what you tried? (Since it sounds like homework ;-)
I suggesting reading Wikipedia: Adder. It gives the schematics for a full-adder using a combination of AND/OR/XOR gates. Note that these gates can be made from just (2-input) NAND gates ... then it's just a matter of minimizing.
Happy learning.
Related
According to another answer, it seems yes, but it looks like any binary counter implementation uses some kind of "clock".
So, is NAND/NOR still turing complete without "clock" component?
For an overview of the topic, this related post is helpful.
A combinational logic circuit composed of NAND and NOR gates without feedback loops is not a Turing complete machine. It lacks memory and it cannot execute a program with loops and conditional branches. The output values only depend on the current input values. Disregarding transient signal changes, such a circuit exhibits a purely static behaviour.
However, SR flip flops as basic elements of sequential logic can be built out of NAND gates. Additional combinational logic determines, how the state machine transitions from one state to the other. Such a finite state machine is still not Turing complete, as it has a finite amount of memory. See this related post.
So, an infinite NAND/NOR circuit could be a candidate to analyze for Turing completeness.
I would like to ask a question about matrix multiplication in HDL. For 6 months I have been learning about FPGAs and ASIC design, but still do not have the enough experience for programming FPGAs using Verilog/VHDL. I had a quick search and found that Verily is suitable for me. Anyway, you just suppose me as a beginner and till now I only followed simple tutorials made of using Xilinx Spartan 3E-XCS1600E MicroBlaze Starter Kit, because I have it, too.
The most challenging part for me was to create matrices in Verilog. If I am able to create matrices and fill them with integers first, then I can move on the next step matrices with floating numbers. In advance, I also want to take inverse of these matrix and seems hard to me extremely.
My question is, what should I do in order to multiply matrices? Is there any tricky or easier way to do that like in C language? (I know Verilog is a HDL and we cannot think on that way). Also how can I convert my floating numbers to fixed or integer type? Then I think I can solve my problem in this way. I looked trough other questions but did not understand well. Thanks for your response and help.
Bonus Question: If I try these operations on MATLAB or Simulink, could it be easier to convert it to HDL using HDL Coder? If it is, could you guide me to do that?
Regards,
Leonardo
You can create matrices with RAM in hardware design. Actually, everything can be described as RAM:)
Of course only integer can be supported in Verilog, but we do have some method that can create and compute float numbers.
Define a float syntax. Suppose that we have reg var[7:0], we can assume var[7:4] is the integer part and var[3:0] is the decimal part. Like 8'b0101_1001 equals 5.9 in DEC. You must limit the range of var[3:0] to 0~9!
IEEE 754. http://grouper.ieee.org/groups/754/ This standard has been widely used in many areas, but I think it will be a little difficult for you.
Deal with a matrices is nothing special, just follow what you have learned in math class.
I'm not good at English. Hope you can understand.
I would like to implement a 8 to 1 multiplexer in FPGA. The inputs of the multiplexers are constants, so I use a look up table instead.
I know that fpgas are made of LUTs. Is there any hardware block that I can use in order to optimize the multiplexer?
Thank you
Not really, unless the each of the 8 "words" you're using is EXTREMELY large and could justify a blockRAM (discussion on when to use a blockRAM here - http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Lut-vs-Block-Ram/td-p/251888 ). If your bus is only 1 bit, or 8 bits wide...just use a case statement. The synthesis & routing stages will take care of converting that "code" into the individual LUTs on the FPGA.
As others have said, ISE is smart enough to infer a mux from your code. You can verify this after running synthesis. Check the Summary in the synthesis report.
If you really want to use LUTs as a good learning exercise, you certainly can do it using a few staged together. Read Understanding the INIT attribute for LUTs to learn how to use the INIT property.
I'm asked to design a true random generator using VHDL.With lot of struggle I could only design a PRNGs not TRNG. Is it possible to generate number perfectly random??? Please suggest me in this. I'm really clueless!
There is NO such thing as a "true" random number generator. This is one of my favorite pseudo-random generators however, and would be fun to implement in VHDL.
http://en.wikipedia.org/wiki/Xorshift
Also, see this: http://en.wikipedia.org/wiki/Random_number_generation#.22True.22_random_numbers_vs._pseudorandom_numbers
The only thing that I can think of to get you "better" randomness would be to do something like write a file and then read a file. The scheduler on the host PC might have enough entropy associated with it to cause some variance in the time it takes for these operations and you could use that time as a key to seed your algorithm.
Since you are asking about VHDL, you want to design special-purpose hardware. Now if you operate hardware in a way which should never be done for digital logic, you might get some kind of "true" random behavior.
If, e.g., you design a circuit with a D-type flip-flop that is clocked when its data input changes its level, the output becomes metastable, i.e. is some time undefined (between 0 and 1), before it becomes stable as 0 or 1 again. How long this takes, depends among others on the electric noise, e.g. is random. I could imagine that you can use such effects to make a random generator.
Contrary to the claims of most of the other answers, there are several TRNG designs for FPGAs mostly based on ring oscillators or self-timed rings, see e.g.
B. Yang, "True Random Number Generators for FPGAs," PhD thesis, KU Leuven, N. Mentens, and I. Verbauwhede (promotors), 2018.
and
VHDL TRNG designs
thank u all for ur replies.I'm thinking to use a register holding different values and take it each time the repetition starts. the idea is to provide different seed values so I can get random values. Since I'm new to VHDL coding, Im not sure if this works but just a try from my side if I can do like this. Any suggestions are welcomed on this.
You're not going to get a true random number generator out of an FPGA / VHDL. The best you can hope for is a h/w PRNG that's readable from some register somewhere.
You might choose to implement one of the PRNG algorithms out there. You're then going to have to trust the algorithm designer and then trust which ever VHDL implementation you go with (your own or one you acquire off someone else). You might start by looking at:
http://en.wikipedia.org/wiki/List_of_pseudorandom_number_generators#Cryptographic_algorithms
Can any one tell what are the differences between these implementations in verilog/VHDl? I mean how does Mealy and Moore Synthesize into circuits in detail ? Any links would prove useful too.
I am quite familiar to this
Thank you
But is this the way it implements ??
The synthesiser will implement logic that matches the code you have written. If you have outputs which are unregistered (ie, not written to from a clocked block) then that's what the synthesiser will give you.
More to the point - why does anyone care? Academics seem to keep teaching Mealy vs Moore for no good reason I can see. In my getting on for 2 decades of professional electronic design, I have never had to care what "kind" of state machine I am getting. I just describe the behaviour and let the tools produce the circuits. The tools also do not care (check the logfiles, it won't say "found a Mealy state-machine" anywhere).
whether or not the synthesizer recognizes your code as FSM and also the way it implements FSMs in hardware depends on the synthesizer you use! check the according documentation. e.g. for Xilinx XST, see the XST user Guide, and search for FSM.
I know this is 3 weeks old, but there's an answer here, with details of what the various styles synthesise to in XST. The example is actually a Moore machine, but some of the styles have combinatorial outputs, which will give you an idea of what will happen for Mealy machines. There are some surprises - XST can push combinatorial outputs back into state registers, for example.