Can any one tell what are the differences between these implementations in verilog/VHDl? I mean how does Mealy and Moore Synthesize into circuits in detail ? Any links would prove useful too.
I am quite familiar to this
Thank you
But is this the way it implements ??
The synthesiser will implement logic that matches the code you have written. If you have outputs which are unregistered (ie, not written to from a clocked block) then that's what the synthesiser will give you.
More to the point - why does anyone care? Academics seem to keep teaching Mealy vs Moore for no good reason I can see. In my getting on for 2 decades of professional electronic design, I have never had to care what "kind" of state machine I am getting. I just describe the behaviour and let the tools produce the circuits. The tools also do not care (check the logfiles, it won't say "found a Mealy state-machine" anywhere).
whether or not the synthesizer recognizes your code as FSM and also the way it implements FSMs in hardware depends on the synthesizer you use! check the according documentation. e.g. for Xilinx XST, see the XST user Guide, and search for FSM.
I know this is 3 weeks old, but there's an answer here, with details of what the various styles synthesise to in XST. The example is actually a Moore machine, but some of the styles have combinatorial outputs, which will give you an idea of what will happen for Mealy machines. There are some surprises - XST can push combinatorial outputs back into state registers, for example.
Related
I have designed the basic unit of the Butterfly PUF. Any suggestion on how to implement it onto the FPGA board?
Have you read this article: https://www.researchgate.net/publication/4349783_Extended_abstract_the_butterfly_PUF_protecting_IP_on_every_FPGA ?
They claim to have implemented a Butterfly PUF on Xilinx's Virtex5 FPGA, and provide some theoretical background.
The catch is that you REALLY must try to make the critical paths as symmetrical as possible, so the resulting delay comes from the production process variations, and not design. It turns out it's not that easy on FPGA, and there are other publications that proves the Butterfly PUF to be "ill suited for the FPGA" -
https://eprint.iacr.org/2009/629.pdf
Anyway, to maintain the control of the paths symmetry you must go deeper - explore the SLICE architecture of your FPGA (what type are you using btw?) surely they have some sort of latch / FF element.
In a recent question (Difference in initializing a state machine between a simulator and synthesizer) I found out that simulators and sythesizers do not always treat VHDL code in exactly the same way. For example, when initialising a state machine using an enumerated type a simulator defaults to the enumerator's left hand value; however, it does not appear so clear cut as to the value a synthesizer defaults to.
Being relatively new to VHDL and FPGAs, it got me wondering as to whether there are other differences between the two that would be useful to know about. Does anyone know of any such differences that they would share? Even links to other places explaining such differences would be useful.
Thanks
I come from Verilog but about the same rules apply.
1/ Do not use any initialization, use a reset.
2/ Do not use sensitivity list. Use always #( * ) or always_comb
I don't know the VHDL equivalent of this one, but I assume somebody will point it out in a comment soon ;-)
3/ Never assume, always know what kind of logic will be generated. If you are not sure, use a different language construct or find out.
4/ Be fussy, meticulous, precise, excessively orderly, the best description is: be anal!
By the way I followed the mentioned post and was somewhat stunned by it. I'll be honest: I don't like VHDL for many reasons and thought the one asset of it was that errors like that where not possible because of the tight type & vector length checking. Obviously not, so the only remaining reason for using VHDL goes out the window for me.
Kind on hard-simple question,
i know it's general but that is exactly why i am asking...
if i write a code in vhdl and i use a process which starts this way:
Process(clk,x,y,x)
begin
...
end process
is there any way which in i won't have to save x,y,z values ? the way i understand this, if i wont save them, i wont be able to say if one of them changed which means i have to save them.
im writing assignment with a friend for university and we have different opinions. thanks a lot for helpers !
It totally depends on your needs.
In case you don't know - when you make some project in VHDL for FPGA, CPLD etc. you have to forget about what you knew about programming, because you are designing hardware, not software. You mostly, if not always, you don't have to save this values, for example when you make combinatorial circuit. In this case you don't care what was before, but only what this value is currently. Look at some examples with finite states machines, that has process with combinatorial logic.
And lastly – if you put clock to sensitivity list, it means that you want it to be synchronous, and process will launch only on some edge of this clock, so putting any more signals to it (with exception for reset) is pointless.
Long story short, a colleague of mine, in charge of the hardware is struggling with the optimization of his VHDL code for his FPGA. I, being much more on the software-side of things, was wondering if there would be something similar to the keyword "volatile" in VHDL (like, for example, in C++).
The idea would be to avoid the compiler to optimize "too much" the code, providing a broken firmware for the FPGA without touching the setting of the environment (in order for the code to be usable on a different design software).
Sorry in advance, if it is a silly question, it was just out of curiosity for me, and maybe the beginning of a solution for my colleague.
Thanks.
No, "volatile" has no place in VHDL.
If he's sharing a variable (as opposed to a signal) between processes, make it a "protected object" (VHDL-2002,2008).
If he's finding synthesis is deleting parts of the design, then they are redundant and cannot affect the result. The problem then is not optimisation, but incorrect VHDL in the first place, which should be better tested in simulation before getting to synthesis.
If he has a specific reason to preserve a named object (signal, etc) through the synthesis process where it is a duplicate of some other signal, then he can attach "keep" or "dont_touch" attributes to it - the exact syntax varies between synthesis tools.
I believe at university I wrote a program for an FPGA which was in a language derived from C. I am aware about languages such as VHDL and verilog. However, what I dont understand is the amount of choice a programmer has regarding which to use? Is it dependent on the FPGA? I am going to be using a Xilinx FPGA.
I am confused because the C-variant language was, unsurprisingly, similar to C- however I know things like VHDL are nothing like C. Therefore if I have a choice I would prefer to programme an FPGA using a C-variant language. The Xilinx website had a million documents and it wasn't overly clear.
It was probably Verilog that you used. It's rather C-like in a lot of it's constructs. I wouldn't say it's "like C", but some syntax is similar.
VHDL is based on ADA, so yes, it's rather different.
There are some small FPGA specific languages around, but VHDL and Verilog are the big two. I think most others have died now.
Remember that writing hardware and writing software are two rather different things. You can't really describe hardware constructs in a language like C (*). The language needs to have special features to allow you to describe exactly what you want. The code needs to be structured in a way that will make the hardware efficient. Don't fool yourself into thinking that you can take a piece of software and magically run it on an FPGA just by changing the language/compiler. (This is targeted more at your follow up question to Marty).
Trying to use C to write a circuit description, is like trying to program a computer in English. You could do it, but it's really the wrong language for the job.
(*) Yes, I know there's SystemC (a C++ class library that is meant to make code synthesisable), but I've yet to see anyone get good results from it, and certainly not on FPGAs. Even then the code has to be structured in a similar way as for an HDL.
Clearly HDL are still preferable when programming FPGA (Xilinx, Altera etc : all accept VHDL or Verilog).
However, things are changing (slowly) : there are now excellent so-called behavioral synthesizers that allow you to code in C and generate hardware, expressed for you in VHDL or Verilog at the register-transfer level. They are sometimes refered as HLS : high-level synthesis.
The problem is that they are quite expensive.
Synfony from Synopsys
Cynthesizer from Forte Design Systems
CatapultC from Calypto (was from Mentor)
ImpulseC
At the academic level :
Gaut from Labsticc lab (France)
spark
legup
Hercules
...
Basically, these tools work by extracting a dependency graph from the C program : nodes represents computations and edges represent variables : that is all what you do when you program, in either C or other programming language. Using this internal representation, the compiler can do hardware-relevant transformations like : register allocation (mapping variables to register, or keeping them combinatorial i.e on wires), operations scheduling (deciding if operation execute in same clock cycle) etc, and finally generate HDL automatically.
Hope this helps
JCLL
Usually FPGA vendors will have toolchains that support both Verilog and VHDL - it's up to you to choose which language you'd like. It's generally just these two languages that are supported.
For more C-like languages, a long-shot option is to use the synthesisable subset of SystemC. This is C++ with circuit-friendly stuff added. I'm not sure if the FGPA tools support this though.