I've been racking my brain on how to do a pitch shift in p5.js, and I've found documentation for a rate change (pitch and speed together), as well as a speed change without changing pitch. I was trying to experiment with having those run simultaneously, but it appears rate() is only available for p5.SoundFile and speed is only available for p5.MediaElement.
I was wondering if anyone had run across a way to extend functionality from one object to another, or if there was a way to manually extend the functionality somewhere in custom code.
Option 1. Switch to ToneJS
ToneJS is another library that wraps the browser's Audio API and it has a built in PitchShift effect. There's nothing special about p5.sound that makes it better or worse for use with p5.js except maybe that it follows some of the same conventions.
Option 2. Write a Custom Effect
p5.Sound provides a base class p5.Effect which could be used to implement a pitch shift effect however, this would be a pretty challenging project unless you have experience with digital signal processing and the underlying browser Audio API. Here's a Wikipedia page on the algorithm in question.
I have instantiated the BSCANE2 in my tutorial designs in order to do easy controls and commands into the trial designs, and in order to simulate this I will use the BSCAN_SIME2.
However, I do not seem to find any documentation on this SIME2.
My trials so far on simulating has shown that it does set the SHIFT signal when going through the DR Shift states, but I have not yet been able to get a SEL signal from issuing a USER1 JTAG instruction.
Anyone had success using this simulation component?
Up until now I have just used very simple structures in my test bench. I dont want to build a larger design before I know exactly how to stimulate it.
Thanks.
In many of my VHDL designs I create a lot of low level components in HDL (which is fine). However, when I am ready to create multiple instantiations and link them together at the top-level, I find that the file ends up being rather large with tons of internal signals going between tons of component instantiations. It gets a little unwieldy and hard to follow.
Instead, I thought what might be easier to understand and faster to develop with is if there was a graphical tool to do the high level component linking. It would be able to parse my low level HDL files and determine the port inputs/outputs and create a block (or multiple instances of that block). I could then use my mouse to create connections between the blocks and give them a text label. When I am done, it would be able to auto-generate a VHDL file with all appropriate syntax for creating internal signals, component instantiations, port declarations, etc.
I tried experimenting with Xilinx Schematic Editor, but this thing was a beast and I did not have any luck.
Is there any tool out there like this? If it could even get me 90% of the way I'd be happy.
You should take a look at www.sigasi.com
Sigasi has autocompletes to help you with the instantiations and quick-fixes to help you with the wiring. There is also a premium version that gives you a live, graphical block diagram view (demo screencast)
I am a newbie to VHDL and can't figure out how to debug VHDL code.
Is there any software that could probably give me an insight to the internal signals of my VHDL entity as time passes or something like that?
Please help.
As the other posts have pointed out, you'll likely need a simulator like GHDL. However, to debug your simulation, there are a few different methodologies:
Classic print statements -- just mix in writeline(output,[...]) in your procedural code. See this hello world example. If you're just getting started, then adding print statements will be invaluable. For most of the simulation debug that I do ( and that is part of my job ), I do almost all of the debug based on print statements that we've built up in our design and testbench. It is only for the final debug, or for more difficult issues that I use the next debug method.
"Dumping" the simulation ( for GHDL see this page and this one ). This is a cycle by cycle trace of your design ( or a subset of your design). It's as if you hook up a logic analyzer to every single wire in your design. All the info you could ever want about your design, but at a very low level -- the signal level. To use this methodology:
Create a simulation "dump". The base format for such a dump is a Value Change Dump or VCD. Whichever simulator you use, you'll need to read the documentation on how to create a VCD. ( You can also search "dump" in your docs -- your simulator may use a different file format for its dumps.)
Once you create a simulation dump, you then load your dump into a wave-form viewer. If you're using the gEDA package, then you would use gtkwave to view the dump.
note If you want to use GHDL and gtkwave to debug your VHDL code, you can install them on ubuntu with command:
% sudo apt-get install geda ghdl
( assuming you have root access to the machine running ubuntu)
Xilinx offers free version of its design suite: http://www.xilinx.com/tools/webpack.htm. Webpack contains VHDL simulator, although last time I tried I've liked ModelSim's simulator better. It might have changed though.
Wepack is also different from ModelSim as it's not only simulator but full-fledged FPGA design suite.
ModelSim's disadvantage is its license -- as far as I'm concerned it's free for students only.
The others mentioned here are likely more appropriate based on cost and availability. However the best HDL/netlist debugger I've used by far is Verdi.
What you are looking for is an VHDL simulator. There are several alternatives to choose from:
Mentors Modelsim
Xilinx ISim
Aldec Riviera and ActiveHDL
Simili
The Simili software is available as a free version with limited performance.
Once you have the simulator installed you need to learn how to use it. Generally you will have to write a testbench in VHDL too, but some of the simulators will let you create the stimuli signals from a graphical user interface. You can find a large number of examples of VHDL-based testbenches on this page: VHDL Tutorials.
In the simulator you are able to visually inspect the state of your design in the waveform viewer and also be able to set breakpoints in your code to debug the design.
Use a simulation software like ModelSim. This kind of software is usually quite expensive. In general if with your vhdl synthethizer you'll get some lightweight variant of it or similar software which is enough for smaller things.
For small jobs which don't push the language spec all the way, GHDL works fine as a simulator IME. As you push things further (and you must, you can't debug any sizeable piece of code just in silicon) you may find you need to spend some money on something like Mentor's Modelsim/Questa or Aldec's ActiveHDL/Riviera.
first i created test bench to test my component, used isim to simulate this test bench, i inserted break points in the main code areas, used the step into button to step into code, or the run button to jump to next break point
same as i am used to do with any programming language
The professional way to “Debug” VHDL is to create a “testbench”. Like everything else VHDL it’s complicated. Here’s a “how to testbench” link: vhdl Testbenches
I am very lazy. I am also not professional. I prefer to do what is known as “forcing”. If you are using Xilinx, ModelSim, or Vivado, then you have the ability to toss your VHDL code into a “simulation”. There you can add signals to a waveform, select those signals (right click on them) and force their values to be ‘0’ or ‘1’. Then after “forcing” your input, run the simulation for a few nanoseconds and look at the output.
im looking for suggestion in which GUI tool is most appropriate for me to use in implementing my study. im using java language. i would like the graphics to simulate a house in which graphical changes apply without user inputs from mouse or keyboards. my user input is in the form of sms. thanks in advance guys. im hoping to animate it or simulate a smart home through the conditions i had set in my program. thnaks!
Your questions is very underspecified. I will assume that you are at the early stages of producing a hand-rolled home automation programs, you probably need:
an environment to let you test the core logic of the system (i.e. "If the system is in state X and I issue command Y, what does it actually do, and will I lose the contents of my freezer?")
an environment to let you test the SMS communications module
you may need a demo mode to show prospecitve customers what it does (this is my best guess at what is being requested here)
Now (3) could fill in for (1), but is a lot more programming effort, so from the start you probably want a simple text interface to do (1).
In general, you almost certainly want a modular system: a core logic system supported by at least two input models (SMS and keyboard), three output models (text debug, graphical demo, and control-line/wireless signals for the actual hardware), and various ancillary stuff (configuration reading, saved state handling). Come to think of it, since you probably need a way to probe the current state of the system, you should make the saved state and condition probe code share a single framework as well.