constant drivers for net, vhdl shiftreg - vhdl

I'm trying to make a shiftregister in vhdl.
My issue is when I try to store values in the regisgter. This is the code that's causing trouble:
architecture behave of chan_mod is
signal adc_shfreg : std_logic_vector(15 DOWNTO 0);
signal dac_shfreg : std_logic_vector(15 DOWNTO 0);
begin
Rcv_adc:
process(mclk, reset)
begin
if rising_edge(mclk) then
if (reset = '0') then
adc_out <= "0000000000000000";
elsif(chan_on = '1' AND subcycle_cntr = "01" AND chan_sel = '0' AND bit_cntr < 16) then
adc_shfreg <= adc_shfreg(14 DOWNTO 0) & adcdat;
end if;
end if;
end process;
adc_out <= adc_shfreg; --compilation error here
the error i get is this:
Error (10028): Can't resolve multiple constant drivers for net
"adc_out[13]" at chan_mod.vhd(40)
dont know if you need to see my ports, but here they are:
entity chan_mod is
Port ( mclk : in std_LOGIC;
reset : in std_logic;
chan_on : in std_logic;
chan_sel : in std_logic;
adcdat : in std_logic;
dacdat : out std_logic;
bit_cntr : in std_logic_vector(4 DOWNTO 0);
subcycle_cntr : in std_logic_vector(1 downto 0);
dac_in : in std_logic_vector(15 DOWNTO 0);
adc_out : out std_LOGIC_vector(15 DOWNTO 0);
rd : in std_logic;
wr : in std_logic);
end chan_mod;
(as you probably guessed a few of these are used later in the code and are therefore not in my code-sample)

Your problem is that you're driving adc_out in the process as well as using a concurrent assignment. You should replace the assignment to adc_out in the reset case with an assignment to adc_shfreg.
architecture behave of chan_mod is
signal adc_shfreg : std_logic_vector(15 DOWNTO 0);
signal dac_shfreg : std_logic_vector(15 DOWNTO 0);
begin
Rcv_adc:
process(mclk, reset)
begin
if rising_edge(mclk) then
if (reset = '0') then
adc_out <= "0000000000000000"; <--- BAD! Replace adc_out with adc_shfreg
elsif(chan_on = '1' AND subcycle_cntr = "01" AND chan_sel = '0' AND bit_cntr < 16) then
adc_shfreg <= adc_shfreg(14 DOWNTO 0) & adcdat;
end if;
end if;
end process;
adc_out <= adc_shfreg; --compilation error here

Related

VHDL-can't add numbers?

Hello I want to build a clock on my ALTERA DE2 that I can adjust the length of by pressing keys.
Now the problem is that when I convert from STD_LOGIC_VECTOR to UNSIGNED the code does not work:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_unsigned.all; Do not use with numeric_std
entity Adjust_Clock_4_buttens is
port(
clk,clk1 : in STD_LOGIC;
minutes_plus, minutes_minus,houres_plus,houres_minus : in STD_LOGIC;
minutes : IN STD_LOGIC_VECTOR(5 downto 0);
houres : IN STD_LOGIC_VECTOR(4 downto 0);
output_minutes : out STD_LOGIC_VECTOR(5 downto 0);
output_houres : out STD_LOGIC_VECTOR(4 downto 0);
LED_0 : OUT STD_LOGIC;
LED_1 : OUT STD_LOGIC;
LED_2 : OUT STD_LOGIC;
LED_3 : OUT STD_LOGIC
);
end entity Adjust_Clock_4_buttens ;
architecture behavioral of Adjust_Clock_4_buttens is
signal button1_r : std_logic_vector(2 downto 0);
signal button2_r : std_logic_vector(2 downto 0);
signal button3_r : std_logic_vector(2 downto 0);
signal button4_r : std_logic_vector(2 downto 0);
-- signal minutes_total : unsigned(5 downto 0) := (others => '0');
-- signal houres_total : unsigned(4 downto 0) := (others => '0');
signal minutes_total : unsigned(5 downto 0);
signal houres_total : unsigned(4 downto 0);
begin
process(clk)
begin
if (rising_edge(clk) )then
minutes_total<=unsigned(minutes);
houres_total<=unsigned(houres);
-- Shift the value of button in button_r
-- The LSB is unused and is there solely for metastability
button1_r <= button1_r(button1_r'left-1 downto 0) & minutes_plus;
button2_r <= button2_r(button2_r'left-1 downto 0) & minutes_minus;
button3_r <= button3_r(button3_r'left-1 downto 0) & houres_plus;
button4_r <= button4_r(button4_r'left-1 downto 0) & houres_minus;
if button1_r(button1_r'left downto button1_r'left-1) = "01" then -- Button1 rising --button1_r[2:1]
minutes_total <= (minutes_total + 1);
LED_0<='1';LED_1<='0';LED_2<='0';LED_3<='0';
elsif button2_r(button2_r'left downto button2_r'left-1) = "01" then -- Button2 rising --button1_r[2:1]
minutes_total <= (minutes_total-1 );
LED_0<='0';LED_1<='1';LED_2<='0';LED_3<='0';
end if;
if button3_r(button3_r'left downto button3_r'left-1) = "01" then -- Button1 rising --button1_r[2:1]
houres_total <= (houres_total + 1);
LED_0<='0';LED_1<='0';LED_2<='1';LED_3<='0';
elsif button4_r(button4_r'left downto button4_r'left-1) = "01" then -- Button2 rising --button1_r[2:1]
houres_total<= (houres_total-1 );
LED_0<='0';LED_1<='0';LED_2<='0';LED_3<='1';
end if;
end if;
end process;
output_minutes <= std_logic_vector(minutes_total);
output_houres <= std_logic_vector(houres_total);
end architecture behavioral ;
So in this code I get the time from another block the problem start when I try to add minutes and hours and for some reason it does not react to pressing of the keys. Could anyone explain maybe why is that?
The problem might be that you only have the clock in the sensitivity list of your process. Try adding the buttons in the sensitivity list, since they drive your if conditions. (Not sure if that's the problem but I guess it's worth a try)
minutes_total<=unsigned(minutes);
is on 2 lines, inside and outside of the process, which generates multiple line drivers, and will not work, ever!
(didn't read the rest of the code, there may be other problems, like hours not taking an e)
Now that it's inside the process, you need to rename minutes_total as minute_source, else you're incrementing the value only for the one clock cycle when you have a button edge!

LFSR doesn't generate random values during simulation

I am new to VHDL, but have some idea. I made this LFSR but don't know why it is stuck between the initial seed value and the other XOR value.
I am working with Altera Quartus 16 Lite and ISim.
library ieee;
use ieee.std_logic_1164.all;
--creating a galois LFSR
entity LFSR is
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
rdm_out : out std_logic_vector(15 downto 0);
rdm_out_a : out std_logic_vector(7 downto 0);
rdm_out_b : out std_logic_vector(7 downto 0);
lfsr_Done : out std_logic --lfsr done
);
end entity LFSR;
architecture behavioral of LFSR is
signal temp_out : std_logic_vector(15 downto 0) := (0 => '1' ,others => '0'); --initial value as seed
signal temp_done : std_logic;
begin
process (clk, rst)
begin
if rising_edge (clk) then --module operates only when enabled
if (rst = '1') then
temp_out <= (0 => '1' ,others => '0');
temp_done <= '0';
elsif (en = '1') then
temp_out <= temp_out(15 downto 11) & (temp_out(10) xor temp_out(0)) & temp_out(9 downto 5) & (temp_out(4) xor temp_out(0)) & temp_out(3 downto 0);
--temp_out <= (temp_out(15) xor temp_out(0)) & (temp_out(14) xor temp_out(0)) & temp_out(13) & (temp_out(12) xor temp_out(0)) & temp_out(11 downto 4) & (temp_out(3) xor temp_out(0)) & temp_out(2 downto 0);
temp_done <= '1';
end if;
end if;
end process;
rdm_out <= temp_out(15 downto 0);
rdm_out_a <= temp_out(15 downto 8);
rdm_out_b <= temp_out(7 downto 0);
lfsr_Done <= temp_done;
end architecture behavioral;`
The commented out temp_out is actual feedback (taps are 16,15,13, and 4) as I checked with random taps but still no improvement.
And the testbench I used is this:
library ieee;
use ieee.std_logic_1164.all;
entity lfsr_tb is
end lfsr_tb;
architecture test_bench of lfsr_tb is
component LFSR
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
rdm_out : out std_logic_vector(15 downto 0);
rdm_out_a : out std_logic_vector(7 downto 0);
rdm_out_b : out std_logic_vector(7 downto 0);
lfsr_Done : out std_logic );
end component;
signal clk1: std_logic;
signal rst1: std_logic;
signal en1 : std_logic;
signal rdm_out1 : std_logic_vector(15 downto 0);
signal rdm_out_a1 : std_logic_vector(7 downto 0);
signal rdm_out_b1 : std_logic_vector(7 downto 0);
signal lfsr_Done1 : std_logic ;
begin
mapping: LFSR port map(
clk => clk1,
rst => rst1,
en => en1,
rdm_out => rdm_out1,
rdm_out_a => rdm_out_a1,
rdm_out_b => rdm_out_b1,
lfsr_Done => lfsr_Done1 );
clock: process
begin
clk1 <= '0'; wait for 10 ps;
clk1 <= '1'; wait for 10 ps;
end process;
reset: process
begin
rst1 <= '1'; wait for 10 ps;
rst1 <= '0';
en1 <= '1'; wait for 800 ps;
end process;
end test_bench;
This is the result I am getting:
Yes it was not shifting but this is one is working now.
temp_out(15) <= temp_out(0);-- shifting bit
temp_out(14) <= temp_out(15);
temp_out(13) <= temp_out(14) xor temp_out(0);
temp_out(12) <= temp_out(13) xor temp_out(0);
temp_out(11) <= temp_out(12);
temp_out(10) <= temp_out(11) xor temp_out(0);
temp_out(9 downto 0) <= temp_out(10 downto 1);
Hope it helps others. Thanks guys

Implementing a 10 bit shift register with led outputs

I am trying to implement the the following shift register
entity MyShiftRegister is
port(
clock: in std_logic;
DataIn: in std_logic_vector (9 downto 0);
Left: in std_logic; --synchronous left rotate
Right: in std_logic; --synchronous right rotate
Load: in std_logic; --synchronous parallel load
Clear: in std_logic; -- synchronous clear
DataOut: out std_logic_vector (9 downto 0);
This is what I have so far
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity question2 is
Port (
led: buffer std_logic_vector (9 downto 0);
clk: in std_logic;
btnu: in std_logic;
btnL: in std_logic;
btnR: in std_logic ;
btnD: in std_logic;
btnC: in std_logic
);
end question2;
architecture Behavioral of question2 is
constant active: std_logic :='1';
constant inactive: std_logic :='0';
constant step_zero: std_logic_vector(9 downto 0) :="0000000000";
constant step_one: std_logic_vector(9 downto 0) :="0000000001";
constant step_two: std_logic_vector(9 downto 0) :="0000000010";
constant step_three: std_logic_vector(9 downto 0) :="0000000100";
constant step_four: std_logic_vector(9 downto 0) :="0000001000";
constant step_five: std_logic_vector(9 downto 0) :="0000010000";
constant step_six: std_logic_vector(9 downto 0) :="0000100000";
constant step_seven: std_logic_vector(9 downto 0) :="0001000000";
constant step_eight: std_logic_vector(9 downto 0) :="0010000000";
constant step_nine: std_logic_vector(9 downto 0) :="0100000000";
constant step_ten: std_logic_vector(9 downto 0) :="0100000000";
signal DataIn: std_logic_vector (9 downto 0):= "1111111111";
signal Load: std_logic := btnD;
signal Reset: std_logic;
signal Left: std_logic:= btnL;
signal Right: std_logic:= btnR;
signal DataOut: std_logic_vector := led (9 downto 0);
signal Clear: std_logic:= btnU;
signal speed_enable: std_logic;
begin
SpeedControl: process (clk)
variable counter: integer range 0 to 10000000;
begin
speed_enable<=not active;
if Reset = Active then
counter:= 0;
elsif (rising_edge (clk)) then
counter := counter + 1;
if (counter=10000000) then
speed_enable<= Active;
counter:=0;
end if;
end if;
end process;
shiftregister: process(clk, clear)
begin
if rising_edge (clk) then
if clear= active then
DataOut <= (others => '0');
elsif load = active then
DataOut <= DataIn ;
elsif Left = active then
DataOut <= DataOut(8 downto 0) & "1" ;
if DataOut = "1000000000" then
clear <= active;
elsif Right = active then
DataOut <= DataOut (9 downto 1) & "1" ;
if DataOut = "0000000001" then
clear <= active;
end if;
end if;
end if;
end if;
end process;
with DataOut select
led <= step_one when "0000",
step_two when "0001",
step_three when "0010",
step_four when "0011",
step_five when "0100",
step_six when "0101",
step_seven when "0110",
step_eight when "0111",
step_nine when "1000",
step_ten when "1001",
step_zero when others;
end Behavioral;
How exactly do I rotate bits left and right and tie that to my led outputs. I was thinking of using a counter and just incrementing and decrementing to shift bits left or right but I'm not sure if that would still be considered a shift register.
thanks
To start:
constant step_nine: std_logic_vector(9 downto 0) :="0100000000";
constant step_ten: std_logic_vector(9 downto 0) :="0100000000";
is incorrect. It should be
constant step_nine: std_logic_vector(9 downto 0) :="0100000000";
constant step_ten: std_logic_vector(9 downto 0) :="1000000000";
But this approach is very error prone anyhow. Lets simplify it:
process(sel)
variable selected_led : natural;
begin
led <= (others => '0');
selected_led := to_integer(unsigned(sel));
if selected_led < led'length then
led(selected_led) <= '1';
end if;
end process;
If the led(selected_led) <= '1'; won't synthesize, you probably have to change it to
for i in 0 to led'length-1 loop
if (i = selected_led) then
led(i) <= '1';
end if;
end loop;
As for using the buffer port. Don't. preferably only use in or out. If you want to read an out port, compile with VHDL-2008, or use a temporary signal in between.
Then note that right and left are keywords in VHDL. you shouldn't use them
What you want is very simple and basic VHDL. Example (using VHDL-2008):
process(clock)
begin
if rising'edge(clock) then
if clear = '1' then
data_out <= (others => '0');
elsif load = '1' then
data_out <= data_in;
elsif right_rotate = '1' then
data_out <= data_out(0) & data_out(data_out'length-1 downto 1);
elsif left_rotate = '1' then
data_out <= data_out(data_out'length-2 downto 0) &
data_out(data_out'length-1);
end if;
end if;
end process;

= can not have such operands in this context

Here's the full error: ERROR:HDLParsers:808 - "C:/Users/vROG/Desktop/.../CacheController.vhd" Line 72. = can not have such operands in this context.
I'd understand how to fix this if I was used '+' or '*', but equal sign?
As you can tell, the code isn't nearly being close to completely, but I can't understand why my second nested if isn't working. I've tried turning dirtyBIT to type int, but it still gives me the same error, which leads me to believe that I made a trivial error somewhere.
FIXED (Using user1155120's advice) However how do I resolve the issue with offset and tag?
architecture Behavioral of CacheController is
signal tagFROMCPU : STD_LOGIC_VECTOR(7 downto 0) := CPU_addr(15 downto 8);
signal indexFROMCPU: STD_LOGIC_VECTOR(2 downto 0) := CPU_addr(7 downto 5);
signal offsetFROMCPU: STD_LOGIC_VECTOR(4 downto 0) := CPU_addr(4 downto 0);
TYPE STATETYPE IS (state_0, state_1, state_2, state_3);
SIGNAL present_state : STATETYPE;
--Variables
signal dirtyBIT: std_logic_vector (7 downto 0);
signal validBIT: std_logic_vector (7 downto 0);
TYPE tag is array (7 downto 0) of STD_LOGIC_VECTOR(7 downto 0);
TYPE offset is array (7 downto 0) of STD_LOGIC_VECTOR(4 downto 0);
signal myTag: tag;
signal myOFFSET : offset;
begin
--STATE MACHINE
process(clk)
begin
if (present_state = state_0) then --Start State : Checks for HIT or MISS, PERFORMS HIT OPERATION or MOVES TO STATE_1
if ((myTag(to_integer(unsigned(indexFROMCPU)) = tagFROMCPU)) then
--HIT
else
present_state <= state_1;
end if;
elsIF (present_state = state_1) then --CHECKS DIRTY BIT. IF 0, LOADS DATA, MOVES TO STATE_0 ELSE move to state_2
if (dirtyBit(to_integer(unsigned(indexFROMCPU))) = '0') then
present_state <= state_0;
else
present_state <= state_2;
end if;
elsIF(present_state = state_2) then -- DIRTY BIT IS 1, SAVES DATA, goes back to STATE_1
present_state <= state_1;
end if;
end process;
end Behavioral;
OLD CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CacheController is
Port (
clk : in STD_LOGIC;
CPU_addr : in STD_LOGIC_VECTOR (15 downto 0);
CPU_WR_RD : in STD_LOGIC;
CPU_CS : in STD_LOGIC;
CPU_RDY : out STD_LOGIC;
SDRAM_Addr : out STD_LOGIC_VECTOR (15 downto 0);
SDRAM_WR_RD : out STD_LOGIC;
SDRAM_MSTRB : out STD_LOGIC;
MUX1,MUX2 : out STD_LOGIC;
SRAM_Addr : out STD_LOGIC_VECTOR (7 downto 0);
SRAM_WEN : out STD_LOGIC
);
end CacheController;
architecture Behavioral of CacheController is
signal tagFROMCPU : STD_LOGIC_VECTOR(7 downto 0) := CPU_addr(15 downto 8);
signal indexFROMCPU: STD_LOGIC_VECTOR(2 downto 0) := CPU_addr(7 downto 5);
signal offsetFROMCPU: STD_LOGIC_VECTOR(4 downto 0) := CPU_addr(4 downto 0);
TYPE STATETYPE IS (state_0, state_1, state_2, state_3);
SIGNAL present_state : STATETYPE;
--Variables to emulate SRAM
TYPE dirtyBIT is array (7 downto 0) of std_logic;
TYPE validBIT is array (7 downto 0) of std_logic;
TYPE tag is array (7 downto 0,7 downto 0) of std_logic;
TYPE offset is array (7 downto 0,4 downto 0) of std_logic;
begin
--STATE MACHINE
process(clk)
begin
if (present_state = state_0) then --Start State : Checks for HIT or MISS, PERFORMS HIT OPERATION or MOVES TO STATE_1
elsIF (present_state = state_1) then --CHECKS DIRTY BIT. IF 0, LOADS DATA, MOVES TO STATE_0 ELSE move to state_2
if (dirtyBit(to_integer(unsigned(indexFROMCPU))) = '0') then
present_state <= state_0;
else
present_state <= state_2;
end if;
elsIF(present_state = state_2) then -- DIRTY BIT IS 1, SAVES DATA, goes back to STATE_1
present_state <= state_1;
end if;
end process;
end Behavioral;
Operator overload resolution (for the "=" operator) requires a function be declared with a matching signature (types of the left and right inputs and the return type).
if (dirtyBit(to_integer(unsigned(indexFROMCPU))) = '0') then
Change the declaration for dirtyBit:
--Variables to emulate SRAM
-- TYPE dirtyBIT is array (7 downto 0) of std_logic;
signal dirtyBIT: std_logic_vector (7 downto 0);
And your code analyzes. I'd suggest the other type declaration (validBIT, tag and offset) should be similarly treated.
It looks like there should be an array type where offset is used. The type name might be changed to preserve offset as a signal name.

VHDL - Writing to FPGA Register

I have an FPGA with four push buttons - the two left most ones should cycle up and down the 16 registers, while the two right most ones should increment and decrement the value stored in this register. Here is my attempt at the code to do this:
entity raminfr is --inferring the RAM here
port (
clk : in std_logic;
we : in std_logic;
a : in unsigned(3 downto 0);
di : in unsigned(7 downto 0);
do : out unsigned(7 downto 0)
);
end raminfr;
architecture rtl of raminfr is
type ram_type is array (0 to 15) of unsigned(7 downto 0);
signal RAM : ram_type;
signal read_a : unsigned(3 downto 0);
begin
U1: entity work.lab1 port map ( --ERROR ON THIS LINE
register_counter => a,
value_counter => di
);
process (clk)
begin
if rising_edge(clk) then
if we = '1' then
RAM(to_integer(a)) <= di;
end if;
read_a <= a;
end if;
end process;
do <= RAM(to_integer(read_a));
end rtl;
--lab1 starts here
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lab1 is
port(
clock : in std_logic;
key : in std_logic_vector(3 downto 0);
value_counter : out unsigned(7 downto 0) ; --value to be written to register
register_counter : out unsigned(3 downto 0) --register to write value to
);
end lab1;
architecture up_and_down of lab1 is --actual button logic here
begin
process(clock)
begin
if rising_edge(clock) then
if (key(3)='0' and key(2)='0' and key(1)='1' and key(0)='0') then
value_counter <= value_counter + "1";
elsif (key(3)='0' and key(2)='0' and key(1)='0' and key(0)='1') then
value_counter <= value_counter - "1";
elsif (key(3)='1' and key(2)='0' and key(1)='0' and key(0)='0') then
register_counter<= register_counter + "1";
elsif (key(3)='0' and key(2)='1' and key(1)='0' and key(0)='0') then
register_counter<= register_counter - "1";
end if;
end if;
end process;
end architecture up_and_down;
I get the error Error (10577): VHDL error at DE2_TOP.vhd(312): actual port "a" of mode "in" cannot be associated with formal port "register_counter" of mode "out"on the line indicated above. It is obvious this is not how I would go about doing what I want to do. Can someone shed some light on this?
Change your point of view: Put the RAM under the Pushbutton-FSM. Not vice versa.
This RAM description should be synthesiable. If not take a look in the Synthesis Guide of your tool vendor.
entity raminfr is --inferring the RAM here
port (
clk : in std_logic;
we : in std_logic;
a : in unsigned(3 downto 0);
di : in unsigned(7 downto 0);
do : out unsigned(7 downto 0)
);
end entity raminfr;
architecture rtl of raminfr is
type ram_type is array (0 to 15) of unsigned(7 downto 0);
signal RAM : ram_type;
begin
process (clk)
begin
if rising_edge(clk) then
if we = '1' then
RAM(to_integer(a)) <= di;
end if;
do <= RAM(to_integer(a));
end if;
end process;
end architecture rtl;
You also forgot to activate the write enable for the RAM.
Maybe you try this code (Always do a simulation first!):
--lab1 starts here
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lab1 is
port(
clock : in std_logic;
key : in std_logic_vector(3 downto 0);
value_counter : out unsigned(7 downto 0); --value to be written to register
ram_data : out unsigned(7 downto 0); --value from 'RAM-register'
register_counter : out unsigned(3 downto 0) --register to write value to
);
end lab1;
architecture up_and_down of lab1 is --actual button logic here
signal value : unsigned(7 downto 0) := (others => '0');
signal ram_a : unsigned(3 downto 0) := (others => '0');
signal ram_we : std_logic;
begin
-- infer your RAM
your_ram: entity work.raminfr
port map (
clk => clock, --: in std_logic;
we => ram_we, --: in std_logic;
a => ram_a, --: in unsigned(3 downto 0);
di => value, --: in unsigned(7 downto 0);
do => ram_data --: out unsigned(7 downto 0)
);
process(clock)
begin
if rising_edge(clock) then
-- default
ram_we <= '0';
-- change value
if key(1) = '1' then
value <= value + 1;
end if;
-- change value
if key(0) = '1' then
value <= value - 1;
end if;
-- change 'register'
if key(3) = '1' then
ram_a <= ram_a + 1;
end if;
-- write value to register
if key(2) = '1' then
ram_we <= '1';
end if;
end if;
end process;
value_counter <= value;
register_counter <= ram_a;
end architecture up_and_down;

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