I want to make a lib file which is using another my lib file. I've tried various combinations in makefile to do linking, but sometimes it asking that linking command ignored or not warning but crashes when I'm trying to use code from libs. My makefile looks like this:
SRC = a.cpp b.cpp c.cpp etc.
OBJ = $(SRC:.cpp=.o)
OUT = ./libHTTPServer.a
INCLUDES := -I/home/myuser/Development/boost_1_51_0 \
-I/home/myuser/Development/HTTPServers/Prot
CCFLAGS = -g
CCC = g++
LIBS = -L/home/myuser/Development/boost_1_51_0/buildedlibs/lib -lm
LDFLAGS = -g
.SUFFIXES: .cpp
.cpp.o:
$(CCC) $(INCLUDES) $(CCFLAGS) -c $< -o $# -lc libProt.a
$(OUT): $(OBJ)
ar rcs $(OUT) $(OBJ)
depend: dep
dep:
makedepend -- $(CCFLAGS) -- $(INCLUDES) $(SRC)
clean:
rm -f $(OBJ) $(OUT)
You can't link libraries to your static library that you're creating. A static library is just a collection of object files packed into an archive.
If libProt is something that you produce yourself and have object files for you could perhaps add them in your ar command to "combine" these two static libraries.
Related
I'm trying to create a makefile for a very basic c++ program. I'm trying to implement the automatic generation of dependencies by running g++ with the -M flag, storing this output in a .d file, and then including those .d files in my main makefile. The makefile content is below
CC=g++
CPPFLAGS=-Wall -Wextra -g -std=c++11
SOURCEDIR=src
SOURCES = $(wildcard $(SOURCEDIR)/*.cpp)
BUILDDIR=build
OBJDIR=$(BUILDDIR)/objs
OBJS=$(SOURCES:$(SOURCEDIR)/%.cpp=$(OBJDIR)/%.o)
DEP_FILES = $(OBJS:.o=.d)
OUTFILE=hello.out
$(OUTFILE) : $(OBJS)
$(CC) -o $# $^ $(CPPFLAGS)
include $(DEP_FILES)
$(OBJDIR)/%.d : $(SOURCEDIR)/%.cpp
$(CC) $(CPPFLAGS) $< -MM -MT $(#:.d=.o) > $#
$(DEP_FILES) : | $(OBJDIR)
$(OBJS): | $(OBJDIR)
$(OBJDIR):
mkdir -p $(OBJDIR)
.PHONY: clean
clean:
rm -f $(BUILDDIR) -r
rm -f *~
rm -f $(OUTFILE)
When I run make, the directory build/objs/ is generated and a .d file is generated with rules in it. Here's main.d file:
build/objs/main.o: src/main.cpp src/main.h
And here's the myfunc.d file:
build/objs/myfunc.o: src/myfunc.cpp src/main.h
Here's the issue
Since I'm calling include on these .d files, I'd expect the .o files which they specify to then be created, and then the main outfile to be created as the main rule. However, make creates the .d files, and then skips directly to the main compilation step without creating any .o files:
g++ -o hello.out build/objs/myfunc.o build/objs/main.o -Wall -Wextra -g -std=c++11
This fails with the following error, since the .o files are never created:
g++: error: build/objs/myfunc.o: No such file or directory
g++: error: build/objs/main.o: No such file or directory
g++: fatal error: no input files
How can I use this makefile to generate the .o files necessary for g++? Thank you for any help in advance!
I saw you got your makefile working but I just wanted to add a few things you might want to consider for future projects. I recommend using the vpath variable rather than specifying $(OBJDIR)/%.o in your makefile recipes. I actually read somewhere that it's not "cannon" to build object files in a separate directory, but in the cursory search I conducted before posting, I couldn't find the document.
That being said, I wrote a makefile that does what you wanted; it builds the output folder, generates the dependencies, and compiles the program. I specifically included the $(COMPILE.cpp) definition so you could see what it's composed of. $(CC) is specifically the C compiler, and $(CFLAGS) is specifically flags for the C compiler. They're just variables, obviously, so you can change them like you did and it will work fine, but the main think to keep in mind is that whoever uses your programs will expect to be able to configure the compilation as they see fit. This means they will set the $(CXX) and $(CXXFLAGS) expecting to set the C++ compiler and flags. $(CPPFLAGS) stands for C/C++ Preprocessor flags.
It's not the cleanest makefile, and if I was to change something, I would just compile the object files in place and save myself that headache. That cuts down on unnecessary make hacking, but for the purposes of answering your question, here it is. Anyways I hope this helps you somewhat, let me know if you have any questions.
Oh yea, I almost forgot; notice I changed your make clean script. I used $(RM) instead of simply rm -f. When you use utilities in your makefiles, you want to use them as variables. Again, this is to allow your users as much freedom and flexibility as possible when they're compiling your program.
vpath %.cpp src
vpath %.hpp include
vpath %.o build/objs
vpath %.d build/objs
.SUFFIXES:
.SUFFIXES: .cpp .hpp .o .d
SRCDIR = src
INCLUDESDIR = include
BUILDDIR = build
OBJDIR = $(BUILDDIR)/objs
SRCS = $(wildcard $(SRCDIR)/*.cpp)
OBJS = $(patsubst %.cpp, %.o, $(notdir $(SRCS)))
DEP_FILES = $(patsubst %.o, %.d, $(OBJS))
INCLUDE_DIRS = -I $(INCLUDESDIR)
CXX = g++
CPPFLAGS =
CXXFLAGS = -Wall -Wextra -g -std=c++11
PROGRAM = hello.out
COMPILE.cpp = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(INCLUDE_DIRS) $(TARGET_ARCH)
all: $(PROGRAM)
$(PROGRAM): %: $(OBJS)
$(LINK.cpp) $(INCLUDE_DIRS) $(addprefix $(OBJDIR)/, $^) $(LOADLIBES) $(LDLIBS) -o $#
%.o: %.cpp
$(COMPILE.cpp) -c -o $(OBJDIR)/$# $<
%.d: %.cpp
mkdir -p $(OBJDIR)
$(COMPILE.cpp) $^ -MM -MT $(addprefix $(OBJDIR)/, $(#:.d=.o)) > $(OBJDIR)/$#
include $(DEP_FILES)
.PHONY: clean
clean:
#echo $(RM)
$(RM) $(BUILDDIR) -r
$(RM) *~
$(RM) $(PROGRAM)
For anyone having a similar issue, here's the correct solution is in the comments. Here for convenience: The included .d files generate dependencies but not a recipe for making the .o files, and since I'm putting things in various directories the default rule doesn't work here, so the .o files aren't created. The solution was to add in the following rule to my main makefile.
$(OBJDIR)/%.o :
$(CC) -c -o $# $< $(CPPFLAGS)
Thanks Matt and Renaud for your answers!
I have makefile that builds shared library libsimpletron.so:
#shell
MKDIR_P = mkdir -p
#compiler
CC = g++
#cpp flags
FLAGS = -std=c++1z
CPPFLAGS = -fPIC -Wall -Wextra
LDFLAGS = -shared
#directories
INC_DIR = ../inc
LIB_DIR = ../lib
BIN_DIR = ../bin
OBJ_DIR = ./obj
ALG_DIR = ./algebra
SOURCES = $(shell echo *.cpp)
HEADERS = $(shell echo $(INC_DIR)/*.h)
_OBJECTS = $(SOURCES:.cpp=.o)
OBJECTS = $(patsubst %,$(OBJ_DIR)/%,$(_OBJECTS))
ALGEBRA = $(LIB_DIR)/libalgebra.so
TARGET = $(LIB_DIR)/libsimpletron.so
.PHONY: directories
all : directories $(ALGEBRA) $(TARGET)
directories: $(OBJ_DIR) $(BIN_DIR) $(LIB_DIR)
$(OBJ_DIR):
$(MKDIR_P) $(OBJ_DIR)
$(BIN_DIR):
$(MKDIR_P) $(BIN_DIR)
$(LIB_DIR):
$(MKDIR_P) $(LIB_DIR)
$(ALGEBRA):
$(MAKE) -C $(ALG_DIR)
$(OBJ_DIR)/%.o: %.cpp $(HEADERS)
$(CC) -c $(FLAGS) $(CPPFLAGS) -o $# $<
$(TARGET) : $(OBJECTS)
$(CC) $(LDFLAGS) -o $# $^
.PHONY: clean
clean:
rm -f $(OBJ_DIR)/*.o
make command builds library successfully (I think) :
g++ -c -std=c++1z -fPIC -Wall -Wextra -o obj/builder.o builder.cpp
...similar lines for each .cpp file...
g++ -shared -o ../lib/libsimpletron.so obj/builder.o obj/gradient_trainer.o obj/layer.o obj/neuron.o obj/perceptron.o obj/simpletron.o obj/trainer.o
Then I am trying to use this library. I compile my test xor as follows:
#compiler
CC = g++
#cpp flags
FLAGS = -std=c++1z
PUGI = -l pugixml
#directories
LIB_DIR = /home/lrdprdx/Projects/SimplePerceptron/lib
SIMPLETRON = -lsimpletron
ALGEBRA = -lalgebra
XOR = xor
SOURCE = xor.cpp
#config file
CONFIG = config.xml
$(XOR) : $(SOURCE) $(CONFIG)
$(CC) $(FLAGS) -L$(LIB_DIR) $(SIMPLETRON) $(ALGEBRA) $(PUGI) -o $(XOR) $(SOURCE)
But when I try to compile this I get errors of undefined reference to .... OK, though I do not understand why those errors exist, I found that adding a .cpp file with an empty main function to the directory with other .cpp files fixes all the stuff:
//empty.cpp
int main()
{
return 0;
}
And after rebuild the shared library I make and execute xor successfully.
The question is: what is going on here?
I doubt that adding the extra file really fixed anything. Most likely some other side-effect helped.
Your problem is that your link line is incorrect. GCC, like most UNIX linkers, is a single-pass linker. That means it only walks all the libraries one time looking for unresolved symbols. And that means that the order of the arguments to the linker is critically important: you have to ensure that if item A references symbols in item B, that A comes before B on the link line.
In your example, you are putting all your libraries first, and your source files last. So, when make starts looking at your libraries it hasn't seen your sources yet, and there are no symbols it needs to link. By the time it compiles your sources, there are no libraries left to resolve symbols from.
Your link line should be arranged with sources and object files first, then libraries (in referencer ... referencee order):
$(CC) $(FLAGS) $(SOURCE) -L$(LIB_DIR) $(SIMPLETRON) $(ALGEBRA) $(PUGI) -o $(XOR)
I have a make file, which creates obj files for all source files and then the executable using those obj files (basically compiling each individual file and then linking all of them together).
CC = gcc
SRC_DIR = src
INC_DIR = inc
OBJ_DIR = obj
CFLAGS = -c -Wall -I$(INC_DIR)
EXE = project
SRCS = $(SRC_DIR)/main.c $(SRC_DIR)/file1.c # and so on...
OBJS = $(OBJ_DIR)/main.o $(OBJ_DIR)/file1.o # and so on...
main : clean build
build: $(OBJS)
$(CC) $(OBJS) -o $(EXE)
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.c
$(CC) $(CFLAGS) -c $< -o $#
I tried to do the same for gtk+3.0 but haven't been successful as the examples on the web always have been with respect to the example file and not the project as a whole (consisting multiple source files). one such eg:
$ cc `pkg-config --cflags --libs gtk+-3.0` hello.c -o hello
Make file for gtk+ is:
CC = gcc
SRC_DIR = .
INC_DIR = .
OBJ_DIR = Obj
CFLAGS = -Wall -g -o
PACKAGE = `pkg-config --cflags --libs gtk+-3.0`
LIBS = `pkg-config --libs gtk+-3.0`
EXE = Gui
SRCS = $(SRC_DIR)/main.c
OBJS = $(OBJ_DIR)/main.o
main : clean build
build: $(OBJS)
$(CC) $(OBJS) -o $(EXE)
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.c
$(CC) $(PACKAGE) $(CFLAGS) $< -o $#
But this doesn't work. It gives errors (undefined reference to 'gtk_init' and other gtk functions)
What modifications should i do?
It should be
LDLIBS = $(shell pkg-config --libs gtk+-3.0)
instead of LIB
Check with make -p your builtin rules.
Look also at this example. See $(LINK.o) variable, etc.
The CFLAGS must have -c or that must be included while compiling. Also, the pkg-config must be included during linking.
After the changes, the make file becomes:
build: $(OBJS)
$(CC) $(CFLAGS) $(OBJS) -o $(EXE) $(LIBS)
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.c
$(CC) $(CFLAGS) ***-c*** -I$(INC_DIR) $< -o $# $(PACKAGE)
The changes run successfully.
This is my VERY FIRST Makefile and so I have cut and paste junk I have found all over the web. My directory structure is pretty flat and was not thought out for Makefiles. It is:
Project/
Project/Control
Project/NodeMgmt
Project/Common
Project/Interfaces
I am writing a Makefile for Control and would like it to standalone inside Control. It needs to include compile and include from Common & Interfaces. Here's my Makefile:
CC = g++
CFLAGS = -Wall -c
INCLUDES = -I/usr/local/include -I/SuperCool/Ion-1.0.0-snapshot-1/include -I/SuperCool/FastrakSDK-4.0.1-snapshot-1/include/Fastrak/Engine/Core/CoreIpc -I/Projects/Common -I/Projects/Interfaces -I/Projects/NodeMgmt -I/Projects/Controller
LFLAGS = -L/usr/local/lib -L/SuperCool/FastrakSDK-4.0.1-snapshot-1/lib
LIBS = -lCoreIpc4 -lIonOs
VPATH = ../Interfaces/
VPATH = ../Common/
VPATH = ../NodeMgmt/
SRCS = *.cc
OBJS = $(SRCS:.cc=.o)
MAIN = controller
.PHONY: clean
all: $(MAIN)
#echo Built Controller
$(MAIN): $(OBJS)
$(CC) $(CFLAGS) $(INCLUDES) -o $(MAIN) $(OBJS) $(LFLAGS) $(LIBS)
.cc.o:
$(CC) $(CFLAGS) $(INCLUDES) -c $< -o $#
clean:
$(RM) *.o $(MAIN)
It's compiling the first .cc file it finds "-c Controller.cc -o *.o" which make sense but that's all it's compiling and I get a *.o output file, not a Controller.o file. It does not compile any other files.
Here's one problem:
SRCS = *.cc
Make doesn't understand wildcards without the wildcard function:
SRCS = $(wildcard *.cc)
That should get it working; we can make minor improvements later.
I wanted to write a makefile for a program that has source files located in different directories, the structure is:
--root(here will be makefile)
--src:
--main.c
--include:
--here are 6 .h files, that are used by other .c files, main.c includes on all of them
--operacje
--suma.c
--iloczyn.c
--roznica.c
--reszta:
macierz.c
--we_wy:
--rest of the .c files
most of .c files include at least one .h file. This is what I wrote so far:
VPATH=./src:./src/include:./src/operacje:./src/reszta:./src/we_wy
CLFAGS = -Wall
CC = gcc
INCLUDE = -I src/include
NAME = macierze
FILE_SOURCE := pliki.c wczytaj_plik.c wypisz_plik.c
CONSOLE_SOURCE := wczytaj_konsola.c wypisz_konsola.c
OTHER_SOURCE := suma.c roznica.c iloczyn.c macierz.c
HEADERS := suma.h roznica.h iloczyn.h wypisz.h wczytaj.h macierz.h
FILE_OBJECTS := $(FILE_SOURCE:.c=.o)
CONSOLE_OBJECTS := $(CONSOLE_SOURCE:.c=.o)
OTHER_OBJECTS := $(OTHER_SOURCE:.c=.h)
%.o: %.c %.h
gcc $(CFLAGS) $(INCLUDE) -c $?
%.o: %.c
gcc $(CFLAGS) $(INCLUDE) -c $? -o $#
finput: HEADERS+=pliki.h
finput: $(FILE_OBJECTS) $(OTHER_OBJECTS) main.o
gcc $(CFLAGS) -o $(NAME) $^ -D WEWY_PLIKI
main.o: main.c $(HEADERS)
gcc $(CFLAGS) $(INCLUDE) -c src/main.c
clean:
rm -rf *.o
The goal is, to make compiled program run a bit differently based on make , hence the -D option and adding
finput: HEADERS+=pliki.h
this finput is the first of the 4 possible options. Each option will be using slightly different set of .c and .h files
Now, when I do
make finput
i get the listing:
gcc -I src/include -c ./src/we_wy/pliki.c ./src/include/pliki.h
gcc -I src/include -c ./src/we_wy/wczytaj_plik.c -o wczytaj_plik.o
gcc -I src/include -c ./src/we_wy/wypisz_plik.c -o wypisz_plik.o
gcc -I src/include -c src/main.c
gcc -o macierze pliki.o wczytaj_plik.o wypisz_plik.o ./src/include/suma.h ./src/include/roznica.h ./src/include/iloczyn.h ./src/include/macierz.h main.o -D WEWY_PLIKI
wczytaj_plik.o: In function `wczytaj':
wczytaj_plik.c:(.text+0x5f): undefined reference to `macierz_alokuj'
main.o: In function `main':
main.c:(.text+0x7e): undefined reference to `suma'
<and other undefined references in main>
I noticed few errors:
1. it doesen't produce .o files from $(OTHER_OBJECTS)
2. there is no -Wall option from $(CFLAGS)
3. and of course it doesen't complete.
I would be grateful for some info, what am I doing wrong.
OTHER_OBJECTS := $(OTHER_SOURCE:.c=.h)
If this is not a typo, it is the explanation for (1.). You rename the files to header files, and the header files are found in VPATH and have no remake rules, so they are included verbatim in $^. Try $(OTHER_SOURCE:.c=.o).
CLFAGS = -Wall
Try CFLAGS instead.
Just to point out that this:
finput: HEADERS+=pliki.h
...
main.o: main.c $(HEADERS)
will not do what you want it to do. Target-specific variables only are in effect inside the recipes of child targets. They do not have any impact on the prerequisite lists (for example).
I urge you to look into methods of automatically generating make dependencies: this is far more efficient (and accurate) than trying to maintain them by hand within the makefile.