I want to define some macros only for some make targets. eg.
all : process1 process2
prcoess1: process1.c process.h
prcoess2: process2.c process.h
%.o:%.c
$(CC) $(CCOPTS) -o $# $<
CCOPTS += -DEXTRA1
extra1 : clean all
CCOPTS += -DEXTRA2
extra2 : clean all
I want macro EXTRA1 to be defined only when I call make extra1. If I call make I don't want EXTRA1 to be defined. How do I accomplish this?
extra1 : CCOPTS += -DEXTRA1
extra1 : clean all
extra2 : CCOPTS += -DEXTRA2
extra2 : clean all
See ยง6.11 Target-specific Variable Values from the GNU make manual.
Related
Background, I suspect XY problem
I have simpler C modules in a directory. I want to write unit tests for these in a sub-directory test/. These unit tests are no more than C programs linking to the module under test, one directory above. I want a Makefile that defines several build targets and lets me build and run the test executables in one step, or separately.
My attempted solution
I've attempted the following:
CC = gcc
CFLAGS = -ggdb -Wall -Wextra -Werror -O3 -std=c99
PARAM_LIST_TARGET = parameter_list_test
PARAM_LIST_SOURCE_FILES = \
../parameter_list.c \
parameter_list_test.c
PARAM_LIST_OBJECT_FILES := $(addsuffix .o,$(basename $(PARAM_LIST_SOURCE_FILES)))
TARGETS = $(PARAM_LIST_TARGET)
all: $(TARGETS)
$(%_TARGET): $(%_OBJECT_FILES)
$(CC) $(CFLAGS) $^ -o $#
.c.o:
$(CC) -c $< -o $# $(CFLAGS)
clean:
$(RM) *.o $(TARGETS)
test: all
#for t in $(TARGETS) ; do ./$$t ; done
This doesn't work, and it's because of the $(%_TARGET): row. Not surprising, I didn't expect it to work, but I hope this illustrates what I'm trying to achieve.
I want to create more chunks of the form _TARGET, _SOURCE_FILES, and _OBJECT_FILES, to test other modules besides PARAM_LIST, for example:
PARAM_LIST_TARGET = parameter_list_test
PARAM_LIST_SOURCE_FILES = \
../parameter_list.c \
parameter_list_test.c
PARAM_LIST_OBJECT_FILES := $(addsuffix .o,$(basename $(PARAM_LIST_SOURCE_FILES)))
OTHER_MODULE_TARGET = other_module_test
OTHER_MODULE_SOURCE_FILES = \
../other_module.c \
other_module_test.c
OTHER_MODULE_OBJECT_FILES := $(addsuffix .o,$(basename $(OTHER_MODULE_SOURCE_FILES)))
I understand that % works on filenames, so attempting to use it on variables fails:
$(%_TARGET): $(%_OBJECT_FILES)
$(CC) $(CFLAGS) $^ -o $#
How can I write a rule that matches the Makefile variables _TARGET to their associated _OBJECT_FILES, without creating one per test target?
Or more importantly, how should I do it totally differently?
Edit: I've seen this, however it seems it's only working with a single source file per executable.
You can always access make variables by constructing their names:
MY_VAR := "my var"
HIS_VAR := "his var"
HER_VAR := "her var"
CATS_VAR := "cats var"
DOGS_VAR := "dogs var"
ALL_PERSONS := MY HIS HER CATS DOGS
ALL_VARS := $(foreach p,$(ALL_PERSONS),$($(p)_VAR))
$(info $(ALL_VARS))
Output:
$ make
"my var" "his var" "her var" "cats var" "dogs var"
Defining the dependencies separately seems to work, thanks to this answer:
TARGETS = $(PARAM_LIST_TARGET) $(OTHER_MODULE_TARGET)
all: $(TARGETS)
$(PARAM_LIST_TARGET): $(PARAM_LIST_OBJECT_FILES)
$(OTHER_MODULE_TARGET): $(OTHER_MODULE_OBJECT_FILES)
$(TARGETS):
$(CC) $(CFLAGS) $^ -o $#
This eliminates the need for a duplicate rule (one per target). Still, the definition of dependencies for each target looks like duplicates, a pattern match for these would be nice.
More than that, the OBJECT_FILES variable becomes unnecessary. This works:
PARAM_LIST_TARGET = parameter_list_test
PARAM_LIST_SOURCE_FILES = \
../parameter_list.c \
parameter_list_test.c
$(PARAM_LIST_TARGET): $(addsuffix .o,$(basename $(PARAM_LIST_SOURCE_FILES))) # The dependencies directly
It would still feel nice to have this last row as one rule for all targets. Something like "for all variables ending with TARGET, build a dependency to the content of the variable with the same name, but ending with SOURCE_FILES instead".
I'm writing a Makefile using static pattern rules and I want for each element of TARGETS a variable assigned to the current target name (here the stem '%').
TARGETS = a b c d
all : $(TARGETS)
$(TARGETS) : % : DIR = %
$(TARGETS) : % : %_setup build
a_setup :
code for a
b_setup :
code for b
...
build
code using "DIR = XX" previously configured
but gnumake complains about the target-specific variable DIR:
make: *** No rule to make target 'DIR', needed by 'a'
Is it possible to mix static pattern rules and variable assignation? Thanks!
According to the GNU make manual you can't do it like that. However, you can use $#. In you example you can directly assign DIR=$# but more generally you can use $# in combination with patsubst:
TARGETS = a b c d
all : $(TARGETS)
$(TARGETS) : DIR = $(patsubst %,%,$#)
$(TARGETS) : % : %_setup build
echo $#: DIR:$(DIR)
%_setup :
echo $#
build:
echo $#
I have a makefile where a variable $DEBUG decides whether to build for deployment or debugging. There is one main Makefile, and multiple platform-specific makefiles that get included. I want the variable $DEBUG to be set to 1 automatically when the target test is built.
The main makefile:
DEBUG := 0
test : override DEBUG := 1
DIST_DIR := dist/
ifeq ($(DEBUG), 1)
BUILD_DIR := build/debug
else
BUILD_DIR := build/deploy
endif
# detect operating system
ifeq ($(OS), Windows_NT)
UNAME := Windows
else
UNAME := $(shell uname -s)
endif
# include platform-specific Makefile
export
ifeq ($(UNAME), Darwin)
include Makefile.darwin
endif
ifeq ($(UNAME), Linux)
include Makefile.linux
endif
And the platform-specific Makefile.linux:
...
CXX := clang++-3.8
CXXFLAGS := -std=c++14 -fPIC -I./external/include -fcolor-diagnostics
LDFLAGS :=
LDLIBS := -lpthread -lm
ifeq ($(DEBUG), 1)
CXXFLAGS += -g
else
CXXFLAGS += -O3 -DNDEBUG
endif
...
all : $(TARGET)
test : $(TEST_TARGET)
$(TEST_TARGET)
So there are two rules for test: One in the main makefile sets the target-specific variable $DEBUG, and the one in Makefile.linux builds the test. The variables used for building ($CXXFLAGS, $BUILDDIR, and others) are set before the rules, and use conditionals.
Everything in the makefiles is working correctly, however calling make test does not alter the variable $DEBUG: both $CXXFLAGS and $BUILDDIR still get set to the values they would have for a deployment built.
Is there a way to first set $DEBUG := 1 in Makefile when the target is test, and then normally proceed?
Or is there a special variable that contains the target name, for example
ifeq ($(MAKEFILE_TARGET), test)
...
endif
test : override DEBUG := 1 doesn't work because it declares a target-specific variable that is only visible within that recipe.
There does exist a variable containing the target names that were specified at the command line: MAKECMDGOALS. Note that it doesn't include the default target if it wasn't explicitly specified at the command line.
Example makefile:
DEBUG := $(filter test,$(MAKECMDGOALS))
all:
#echo all : $(MAKECMDGOALS) : $(DEBUG) : $(if $(DEBUG),1,0)
test:
#echo test : $(MAKECMDGOALS) : $(DEBUG) : $(if $(DEBUG),1,0)
Usage:
$ make
all : : : 0
$ make all
all : all : : 0
$ make test
test : test : test : 1
$ make all test
all : all test : test : 1
test : all test : test : 1
One simple option is to have your test target recursively invoke make with DEBUG=1. That works with included makefiles as well. Example:
DEBUG := 0
test:
make DEBUG=1
DIST_DIR := dist/
...
In trying to implement nonrecursive make, I have a Rules.mk which looks like:
############
# Enter Stack
############
sp := $(sp).x
dirstack_$(sp) := $(d)
d := $(dir)
.. setup things like OBJECTS_$(d), DEPS_$(d), TARGET_$(d), etc ...
############
# Exit Stack
############
-include $(DEPS_$(d))
d := $(dirstack_$(sp))
sp := $(basename $(sp))
One of the variables I wanted to set was:
INCLUDE_PATH_$(d) := -Isomething -Isomething/else ...
To be used in the compilation rule:
$(OBJDIR_$(d))/%.o : $(d)/%.cpp $(OBJDIR_$(d))/%.d
$(CC) $(CFLAGS) $(INCLUDE_PATH_$(d)) -o $# -c $<
But this doesn't work - $(INCLUDE_PATH_$(d)) doesn't get expanded until later - when $(d) is no longer has the value I need it to have in order for this to work. What's the way for me to do this properly?
You could use a target-specific variable
$(OBJDIR_$d)/%.o : INCLUDES := $(INCLUDE_PATH_$d)
$(OBJDIR_$d)/%.o : $d/%.cpp $(OBJDIR_$d)/%.d
$(CC) $(CFLAGS) $(INCLUDES) -o $# -c $<
The following is perhaps more standard / flexible (assuming CPPFLAGS isn't set to recursively expand) although it depends on your needs
$(OBJDIR_$d)/%.o : CPPFLAGS += $(INCLUDE_PATH_$d)
$(OBJDIR_$d)/%.o : $d/%.cpp $(OBJDIR_$d)/%.d
$(CC) $(CPPFLAGS) $(CFLAGS) -o $# -c $<
Does anyone know what is wrong with my Makefile?
CXX = g++ # compiler
CXXFLAGS = -g -Wall -MMD # compiler flags
MAKEFILE_NAME = ${firstword ${MAKEFILE_LIST}} # makefile name
OBJECTS1 = utf.o # object files forming executable
EXEC1 = utf # executable name
OBJECTS2 = driver.o rational.o # object files forming executable
EXEC2 = rational # executable name
OBJECTS3 = da.o qa.o pa.o ua.o # object files forming executable
EXEC3 = ho # executable name
OBJECTS = ${OBJECTS1} ${OBJECTS2} ${OBJECTS3}
EXECS = ${EXEC1} ${EXEC2} ${EXEC3}
DEPENDS = ${OBJECTS:.o=.d} # substitute ".o" with ".d"
.PHONY : all clean
all : ${EXECS}
${EXEC1} : ${OBJECTS1} # link step
${CXX} $^ -o $#
${EXEC2} : ${OBJECTS2} # link step
${CXX} $^ -o $#
${EXEC3} : ${OBJECTS3} # link step
${CXX} $^ -o $#
${OBJECTS} : ${MAKEFILE_NAME} # OPTIONAL : changes to this file => recompile
-include ${DEPENDS} # include *.d files containing program dependences
clean : # remove files that can be regenerated
rm -f ${DEPENDS} ${OBJECTS} ${EXECS}
Error:
./Makefile: 1: CXX: not found
./Makefile: 2: CXXFLAGS: not found
./Makefile: 3: Bad substitution
use the make command to run the Makefile. you can specify a target for make, like make all.
Don't execute the makefile on its own. Your shell is trying to treat it as a shell script of some kind.
Run make, which uses the makefile.