I have a makefile where a variable $DEBUG decides whether to build for deployment or debugging. There is one main Makefile, and multiple platform-specific makefiles that get included. I want the variable $DEBUG to be set to 1 automatically when the target test is built.
The main makefile:
DEBUG := 0
test : override DEBUG := 1
DIST_DIR := dist/
ifeq ($(DEBUG), 1)
BUILD_DIR := build/debug
else
BUILD_DIR := build/deploy
endif
# detect operating system
ifeq ($(OS), Windows_NT)
UNAME := Windows
else
UNAME := $(shell uname -s)
endif
# include platform-specific Makefile
export
ifeq ($(UNAME), Darwin)
include Makefile.darwin
endif
ifeq ($(UNAME), Linux)
include Makefile.linux
endif
And the platform-specific Makefile.linux:
...
CXX := clang++-3.8
CXXFLAGS := -std=c++14 -fPIC -I./external/include -fcolor-diagnostics
LDFLAGS :=
LDLIBS := -lpthread -lm
ifeq ($(DEBUG), 1)
CXXFLAGS += -g
else
CXXFLAGS += -O3 -DNDEBUG
endif
...
all : $(TARGET)
test : $(TEST_TARGET)
$(TEST_TARGET)
So there are two rules for test: One in the main makefile sets the target-specific variable $DEBUG, and the one in Makefile.linux builds the test. The variables used for building ($CXXFLAGS, $BUILDDIR, and others) are set before the rules, and use conditionals.
Everything in the makefiles is working correctly, however calling make test does not alter the variable $DEBUG: both $CXXFLAGS and $BUILDDIR still get set to the values they would have for a deployment built.
Is there a way to first set $DEBUG := 1 in Makefile when the target is test, and then normally proceed?
Or is there a special variable that contains the target name, for example
ifeq ($(MAKEFILE_TARGET), test)
...
endif
test : override DEBUG := 1 doesn't work because it declares a target-specific variable that is only visible within that recipe.
There does exist a variable containing the target names that were specified at the command line: MAKECMDGOALS. Note that it doesn't include the default target if it wasn't explicitly specified at the command line.
Example makefile:
DEBUG := $(filter test,$(MAKECMDGOALS))
all:
#echo all : $(MAKECMDGOALS) : $(DEBUG) : $(if $(DEBUG),1,0)
test:
#echo test : $(MAKECMDGOALS) : $(DEBUG) : $(if $(DEBUG),1,0)
Usage:
$ make
all : : : 0
$ make all
all : all : : 0
$ make test
test : test : test : 1
$ make all test
all : all test : test : 1
test : all test : test : 1
One simple option is to have your test target recursively invoke make with DEBUG=1. That works with included makefiles as well. Example:
DEBUG := 0
test:
make DEBUG=1
DIST_DIR := dist/
...
Related
I am trying to build a dummy C project using GNU Make. I use the following rules to build the object files from the c files and the output from the object files :
AT := #
#Initial tools to get the absolute paths.
TOOLSDIR := ./tools/bin
SHELL := $(TOOLSDIR)/sh
CYGPATH := $(TOOLSDIR)/cygpath
# Defining used tools
TOOLSDIR := $(shell $(CYGPATH) -am "$(TOOLSDIR)")
SCRIPTDIR := $(shell $(CYGPATH) -am "$(SCRIPTDIR)")
LIBDIR := $(shell $(CYGPATH) -am "$(LIBDIR)")
#Defining Env Variable responsible for Removing non-ansi characters in error output
LC_ALL=C
SHELL := $(shell $(CYGPATH) -am "$(SHELL)")
CYGPATH := $(shell $(CYGPATH) -am "$(CYGPATH)")
TEST := $(shell $(CYGPATH) -am "$(TOOLSDIR)/test")
RM := $(shell $(CYGPATH) -am "$(TOOLSDIR)/rm") -f
PERL := $(shell $(CYGPATH) -am "$(TOOLSDIR)/perl")
FIND := $(shell $(CYGPATH) -am "$(TOOLSDIR)/find")
MKDIR := $(shell $(CYGPATH) -am "$(TOOLSDIR)/mkdir")
PERL5LIB := $(LIBDIR)/perl5/site_perl/5.14/x86_64-cygwin-threads;$(LIBDIR)/perl5/site_perl/5.14;$(LIBDIR)/perl5/5.14/x86_64-cygwin-threads;$(LIBDIR)/perl5/5.14
# Defining perl script to convert dependencies genereted by the compiler to unix path
FIXDEPS_SCRIPT := "$(SCRIPTDIR)/fixdeps.pl"
ZAPEXEC_SCRIPT := "$(SCRIPTDIR)/ZAP_Command.pl"
DEPFIX := $(PERL) $(FIXDEPS_SCRIPT)
ZAPEXE := $(PERL) $(ZAPEXEC_SCRIPT)
CREATE_IAR_PROJ := $(PERL) $(IARWKSP_SCRIPT)
COMP_DIR :=C:\ghs\comp_201355
OBJDIR :=.
CC := "$(COMP_DIR)/ccrh850.exe"
AS := "$(COMP_DIR)/ccrh850.exe"
LD := "$(COMP_DIR)/ccrh580.exe"
GSREC := "$(COMP_DIR)/gsrec.exe"
GMEM := "$(COMP_DIR)/gmemfile.exe"
CEXT :=c
CCEXT :=C
ASMEXTC := S
ASMEXTS := s
ASMEXT := 850
ASMEXT_DEFAULT := asm
DBGEXT := dla
DBGEXT_DEFAULT := dnm
OBJEXT := o
EXEEXT := elf
LSTEXT := lst
DEPEXT := dd
INCOPT := -I
EXEMAP := ./exe/PROJECT_NAME.map
CFLAGS :=-c -G -Onone -no_callt -sda=all -large_sda -reserve_r2 -Wundef --short_enum -dual_debug \
-delete -preprocess_assembly_files --no_wrap_diagnostics -registermode=32 -keeptempfiles -prepare_dispose -ansi \
-full_debug_info -noobj -Wimplicit-int -Wshadow -Wtrigraphs -inline_prologue -DOS_MEMMAP=0 -DOS_MULTICORE=OS_SINGLE \
-DOS_USE_CLZ_QUEUE_ALGORITHM=1 -DOS_DEVELOPMENT_SANITY_CHECKS=0 -DOS_KERNEL_TYPE=OS_FUNCTION_CALL -DOS_USE_TRACE=0 -MD \
-DAUTOSAR_USED -DRENESAS -DF1K -DR7F701583xAFP --long_long -cpu=rh850 -DTS_ARCH_FAMILY=TS_RH850 \
-DTS_ARCH_DERIVATE=TS_RH850F1L -DRH850F1L=1 -DOS_CPU=OS_RH850F1L -DOS_TOOL=OS_ghs -DOS_ARCH=OS_RH850
VPATH :=./ ./obj ./src ./exe
INCLUDES :=-I"./" -I"./obj" -I"./src" -I"./exe"
OBJECTS :=./obj/main.o
.PHONY: all release debug
EXEC := ./exe/PROJECT_NAME.hex
EXEOUT := ./exe/PROJECT_NAME.out
all: debug release
release: $(EXEC)
debug: release
$(EXEC): $(EXEOUT)
#echo '************************************'
#echo 'Using GSREC to Convert .out to .hex'
$(AT)$(GSREC) -o$(EXEC) $(EXEOUT)
#echo 'Generation Done'
#echo '************************************'
$(EXEOUT): $(OBJECTS)
#echo '************************************'
#echo 'Building .out file'
#echo $(EXEOUT)
$(AT)$(CC) $(LDFLAGS) -o $(EXEOUT) $(OBJECTS)
#echo '************************************'
$(OBJDIR)/%.$(OBJEXT): %.$(CEXT)
#echo 'Compiling: $<'
$(AT)$(CC) $(CFLAGS) $(INCLUDES) -filetype.c $(shell $(CYGPATH) -am "$<") -o $#
The output when I execute the target all is as follows :
make: *** No rule to make target 'obj/main.o', needed by 'exe/PROJECT_NAME.out'. Stop.
The main.c source file has the following code :
#include <stdio.h>
#include <stdlib.h>
#include "alpha.c"
void second(void);
int main()
{
printf("Second module, I send you greetings!n");
second();
return 0;
}
The alpha.c source file has the following code :
#include <stdio.h>
void second(void)
{
puts("Glad to be here!");
}
Where $(OBJECTS) is the relative path of all the object files that are supposed to be generated and $(EXEC) and $(EXEOUT) are the outputs. The VPATH contains relative paths. All the needed prerequisites (.c and.h files) can be found among the paths in VPATH and in INCLUDES in the compilation command. That is the exact code I use to build this dummy project which contains only two .c files main.c and alpha.c and main.c uses alpha.c. When the source files are in the same folder as the makefile this dummy project builds, but when I put the source files in the src folder and create a obj folder for the object files to be generated in and an exe folder for the final output to be generated in previously mentioned error appears. What could be the reason for the previously mentioned error?
#Beta is right that it's generally a bad idea to dump a huge makefile into StackOverflow and ask someone to fix it. You should instead try to reduce the problem as much as possible.
However in this case, your problem is here:
OBJDIR :=.
OBJECTS :=./obj/main.o
$(EXEOUT): $(OBJECTS)
...
$(OBJDIR)/%.$(OBJEXT): %.$(CEXT)
...
So after all the variables have been expanded, you get these rules:
./exe/PROJECT_NAME.out: ./obj/main.o
...
./%.o: %.c
...
Well, when make tries to match the pattern ./%.o with the target to be built ./obj/main.o, the stem % will match obj/main. Then it will try to find %.c which resolves to obj/main.c, which doesn't exist.
You should be using the OBJDIR variable in your OBJECTS variable assignment, like:
OBJECTS :=$(OBJDIR)/main.o
then it will work.
I'm using GNU Make and attempting to design Makefiles using non-recursive approach. The issue I have - there doesn't seem to be a way to limit the scope of variables in different Makefiles.
For example, if I have two Makefiles for modules libA and libB
libA Makefile.inc:
src_dir := libA/src
inc_dir := libA/inc
libB Makefile.inc:
src_dir := libB/src
inc_dir := libB/inc
Then when I include the above Makefiles into a master Makefile
include libA/Makefile.inc
include libB/Makefile.inc
Values in variables src_dir and inc_dir are overwritten by the very last Makefile that was included. OK this is probably expected since variables are global in scope here, and this messes up build commands that use those variables, i.e. build command for libA finds variable values for libB.
A way around it is to create unique variables for each Makefile
libA Makefile.inc:
src_dir_libA := libA/src
inc_dir_libA := libA/inc
libB Makefile.inc:
src_dir_libB := libB/src
inc_dir_libB := libB/inc
This solves the issue, but it's a bit awkward to use, since each variable has to be renamed. Does anyone know if there is a better way to solve this, e.g. if GNU Make has some notion of scope or namespace? I've looked at documentation, but can't seem to find anything of that sort. There are target-specific variables, but they appear to have nasty side-effects.
OK, just to be very specific, below is an example Makefile
dep_all :=
all:
# Begin Makefile.inc for project1
# ------------------------------------------------------------------------------
$(foreach var,$(filter local_%,$(.VARIABLES)),$(eval $(var) := ))
local_src_dir := project1/src
local_obj_dir := project1/obj
local_src := $(local_src_dir)/fileA.c $(local_src_dir)/fileB.c
local_obj := $(patsubst $(local_src_dir)/%.c,$(local_obj_dir)/%.o,$(local_src))
dep_all += $(local_src)
dep_all += $(local_obj)
$(info local_obj="$(local_obj)")
$(local_obj): $(local_obj_dir)/%.o: $(local_src_dir)/%.c
gcc -L$(local_obj_dir) -c -o $# $<
# ------------------------------------------------------------------------------
# End Makefile.inc for project1
# Begin Makefile.inc for project2
# ------------------------------------------------------------------------------
$(foreach var,$(filter local_%,$(.VARIABLES)),$(eval $(var) := ))
local_src_dir := project2/src
local_obj_dir := project2/obj
local_src := $(local_src_dir)/fileX.c $(local_src_dir)/fileY.c
local_obj := $(patsubst $(local_src_dir)/%.c,$(local_obj_dir)/%.o,$(local_src))
dep_all += $(local_src)
dep_all += $(local_obj)
$(info local_obj="$(local_obj)")
$(local_obj): $(local_obj_dir)/%.o: $(local_src_dir)/%.c
gcc -L$(local_obj_dir) -c -o $# $<
# ------------------------------------------------------------------------------
# End Makefile.inc for project2
$(info dep_all="$(dep_all)")
.PHONY: all
all: $(dep_all)
.PHONY: clean
clean:
rm -f project1/obj/* project2/obj/*
If I run it then the -L<object_path> option passed to gcc contains value from the last included Makefile, i.e. when building project1, it runs gcc with -Lproject2/obj, which is not the right object path for this project. This is the problem I'm trying to solve.
mkdir -p project1/{src,obj} project2/{src,obj}
touch project1/src/{fileA.c,fileB.c} project2/src/{fileX.c,fileY.c}
$ make
local_obj="project1/obj/fileA.o project1/obj/fileB.o"
local_obj="project2/obj/fileX.o project2/obj/fileY.o"
dep_all=" project1/src/fileA.c project1/src/fileB.c project1/obj/fileA.o project1/obj/fileB.o project2/src/fileX.c project2/src/fileY.c project2/obj/fileX.o project2/obj/fileY.o"
gcc -Lproject2/obj -c -o project1/obj/fileA.o project1/src/fileA.c
gcc -Lproject2/obj -c -o project1/obj/fileB.o project1/src/fileB.c
gcc -Lproject2/obj -c -o project2/obj/fileX.o project2/src/fileX.c
gcc -Lproject2/obj -c -o project2/obj/fileY.o project2/src/fileY.c
The solution is to name all your variables local to a specific file with some prefix.
For example, I use this_ prefix.
Then, in the beginning of each submakefile those variales which have this_ prefix can be cleared as follows:
$(foreach var,$(filter this_%,$(.VARIABLES)),$(eval $(var) := ))
PS. I use this approach in my implementation of non-recursive makefiles, clearing the variables described in the WIKI here: https://github.com/cppfw/prorab
I think I've just figured out a solution. I was reading "The GNU Make Book" and it states a side effect of target specific variables
Target-specific variables apply not just to a target, but also to all
that target’s prerequisites, as well as all their prerequisites, and
so on. A target-specific variable’s scope is the entire tree of
targets, starting from the target for which the variable was defined.
This is not the behaviour I want, however starting with GNU Make 3.82 there is support for private target specific variables
A target-specific variable is normally defined for a target and all
its prerequisites. But if the target-specific variable is prefixed
with the keyword private, it is defined only for that target, not its
prerequisites.
So the following Makefile seems to work correctly for those private variables
dep_all :=
all:
# Begin Makefile.inc for project1
# ------------------------------------------------------------------------------
inc_dir := project1/inc
src_dir := project1/src
obj_dir := project1/obj
src := $(src_dir)/fileA.c $(src_dir)/fileB.c
obj := $(patsubst $(src_dir)/%.c,$(obj_dir)/%.o,$(src))
# These flags will be overwritten by another Makefile
CFLAGS := -I$(inc_dir)
# These flags will be private and not be overwritten by another Makefile
CFLAGS_priv := -I$(inc_dir) -L$(obj_dir)
dep_all += $(src)
dep_all += $(obj)
# Private target specific variables
$(obj): private CFLAGS_priv:=$(CFLAGS_priv)
$(obj): $(obj_dir)/%.o: $(src_dir)/%.c
gcc $(CFLAGS) $(CFLAGS_priv) -c -o $# $<
# ------------------------------------------------------------------------------
# End Makefile.inc for project1
# Begin Makefile.inc for project2
# ------------------------------------------------------------------------------
inc_dir := project2/inc
src_dir := project2/src
obj_dir := project2/obj
src := $(src_dir)/fileX.c $(src_dir)/fileY.c
obj := $(patsubst $(src_dir)/%.c,$(obj_dir)/%.o,$(src))
# These flags will be overwritten by another Makefile
CFLAGS := -I$(inc_dir)
# These flags will be private and not be overwritten by another Makefile
CFLAGS_priv := -I$(inc_dir) -L$(obj_dir)
dep_all += $(src)
dep_all += $(obj)
# Private target specific variables
$(obj): private CFLAGS_priv:=$(CFLAGS_priv)
$(obj): $(obj_dir)/%.o: $(src_dir)/%.c
gcc $(CFLAGS) $(CFLAGS_priv) -c -o $# $<
# ------------------------------------------------------------------------------
# End Makefile.inc for project2
.PHONY: all
all: $(dep_all)
.PHONY: clean
clean:
rm -f project1/obj/* project2/obj/*
The output is what I wanted, since now for each project I can define private CFLAGS_priv variable that sets -I<dir>, -L<dir> paths and it won't be overwritten by other Makefiles.
$ make
gcc -Iproject2/inc -Iproject1/inc -Lproject1/obj -c -o project1/obj/fileA.o project1/src/fileA.c
gcc -Iproject2/inc -Iproject1/inc -Lproject1/obj -c -o project1/obj/fileB.o project1/src/fileB.c
gcc -Iproject2/inc -Iproject2/inc -Lproject2/obj -c -o project2/obj/fileX.o project2/src/fileX.c
gcc -Iproject2/inc -Iproject2/inc -Lproject2/obj -c -o project2/obj/fileY.o project2/src/fileY.c
I'm hoping this will resolve all issues I had and I don't have to use recursive make with it's various associated pitfalls.
So, this is odd. In my makefile I have
CC:=icc
ifeq ($(CC),icc)
CFLAGS := $(ICCFLAGS)
LIBS := $(LIBS) -openmp
else
CFLAGS := $(GCCFLAGS)
LIBS := $(LIBS) -fopenmp
endif
for make, the condition is false but
CCC:=icc
ifeq ($(CCC),icc)
CFLAGS := $(ICCFLAGS)
LIBS := $(LIBS) -openmp
else
CFLAGS := $(GCCFLAGS)
LIBS := $(LIBS) -fopenmp
endif
here the condition is true, and
CC:=icc
CCC:=$(CC)
ifeq ($(CCC),icc)
CFLAGS := $(ICCFLAGS)
LIBS := $(LIBS) -openmp
else
CFLAGS := $(GCCFLAGS)
LIBS := $(LIBS) -fopenmp
endif
here the condition is false again. What the hell is going on?
It seem that you're either passing CC as a command line option, like:
make CC=...
... or invoking make with -e switch, which forces environment variables to take precedence over the ones defined in Makefile.
You can use origin function to check how the variable has been defined:
CC := icc
$(error CC comes from $(origin CC))
If this prints command line or environment override, then the solution is to use override directive:
override CC := icc
This will set CC variable even if there is another one from command line or environment.
my c++ source file look for a specific variable passed from the makefile. when making a different target, this variable definition is different.
How can I define a variable in Makefile based on target.
Thanks
You can use target-specific variable values, they propagate to target's prerequisites:
all : foo bar
foo : CXXFLAGS += -DFOO
bar : CXXFLAGS += -DBAR
foo bar :
#echo target=$# CXXFLAGS=${CXXFLAGS}
.PHONY : all
Do you mean something like this:
$ cat Makefile
BUILD := debug
cxxflags.debug := -g -march=native
cxxflags.release := -g -O3 -march=native -DNDEBUG
CXXFLAGS := ${cxxflags.${BUILD}}
all :
#echo BUILD=${BUILD}
#echo CXXFLAGS=${CXXFLAGS}
.PHONY : all
Output:
$ make
BUILD=debug
CXXFLAGS=-g -march=native
$ make BUILD=release
BUILD=release
CXXFLAGS=-g -O3 -march=native -DNDEBUG
What about that?
ifeq ($(MAKECMDGOALS),release)
CFLAGS += -O3
else
CFLAGS += -O0 -ggdb
endif
I have a big chunk of my makefile (~50 lines) that needs to be copy-pasted 5 times for different case (the different libraries used). Is it possible to create a function in a makefile and just call that function instead of copy-pasting?
This is an example of what I've tried. Basically this tries to find the right path for an installed library.
define Flags_template
$(1)_include_home := $(HOME)/usr/include
$(1)_include_home_name := $(HOME)/usr/include/$(1)
ifneq ($$(wildcard $($(1)_include_home)/$(2)),)
$(1)_Include := $$($(1)_include_home)
else
ifneq ($$(wildcard $($(1)_include_home_name)/$(2)),)
$(1)_Include := $$($(1)_include_home_name)
endif
endif
CFLAGS += -I$$($(1)_Include)
endef
$(eval $(call Flags_template,stdcout,StdCout.hpp))
.PHONY: test
test:
# stdcout_include_home_name = $(stdcout_include_home_name)
# stdcout_Include = $(stdcout_Include)
# CFLAGS: $(CFLAGS)
Typing "make", I get this output:
# stdcout_include_home_name = /home/nicolas/usr/include/stdcout
# stdcout_Include =
# CFLAGS: -I
It's so close. But note the last "-I", I always get dupplicates, one fully expended, one empty...
I don't understant what needs to be eval'ed, escaped with two $, etc.
How can I achieve this?
Thank you very much.
Does §8.8 of the GNU Make (3.82) manual help?
[...] Although it might seem overly complex to use eval in this example,
rather than just writing out the rules, consider two things: first, the template definition (in
PROGRAM_template) could need to be much more complex than it is here; and second, you
might put the complex, “generic” part of this example into another makefile, then include
it in all the individual makefiles. Now your individual makefiles are quite straightforward.
PROGRAMS = server client
server_OBJS = server.o server_priv.o server_access.o
server_LIBS = priv protocol
client_OBJS = client.o client_api.o client_mem.o
client_LIBS = protocol
# Everything after this is generic
.PHONY: all
all: $(PROGRAMS)
define PROGRAM_template =
$(1): $$($(1)_OBJS) $$($(1)_LIBS:%=-l%)
ALL_OBJS += $$($(1)_OBJS)
endef
$(foreach prog,$(PROGRAMS),$(eval $(call PROGRAM_template,$(prog))))
$(PROGRAMS):
$(LINK.o) $^ $(LDLIBS) -o $#
clean:
rm -f $(ALL_OBJS) $(PROGRAMS)
This Works (For Me)
This is the output from the GNU makefile just below:
stdcout_include_home = /work4/jleffler/usr/include
stdcout_include_home_name = /work4/jleffler/usr/include/stdcout
stdcout_Include = /work4/jleffler/usr/include
CFLAGS: -I/work4/jleffler/include -I/work4/jleffler/usr/include
GNU Makefile
CFLAGS = -I${HOME}/include
define Flags_template
$(1)_include_home := $(HOME)/usr/include
$(1)_include_home_name := $(HOME)/usr/include/$(1)
ifneq ($$(wildcard $$($(1)_include_home)/$(2)),)
$(1)_Include := $$($(1)_include_home)
else
ifneq ($$(wildcard $$($(1)_include_home_name)/$(2)),)
$(1)_Include := $$($(1)_include_home_name)
else
$(1)_Include := Neither $$($(1)_include_home) nor $$($(1)_include_home_name) contains $2
endif
endif
CFLAGS += -I$$($(1)_Include)
endef
$(eval $(call Flags_template,stdcout,StdCout.hpp))
.PHONY: test
test:
#echo stdcout_include_home = $(stdcout_include_home)
#echo stdcout_include_home_name = $(stdcout_include_home_name)
#echo stdcout_Include = $(stdcout_Include)
#echo CFLAGS: $(CFLAGS)
The difference is in the wildcard invocations:
ifneq ($$(wildcard $($(1)_include_home)/$(2)),) # Fails
ifneq ($$(wildcard $$($(1)_include_home)/$(2)),) # Works
I have half an intuition about when double-dollars and when single-dollars are needed; I am not sure I can articulate the decision, though.