I have been given an already working Makefile which is actually working fine.
Makefile Contents can be found here in this post ...
Questions about Makefile - what is "$+" & where are .c files/dependencies called here ?
I am asking this question separately from my previous post mentioned above as it involves a different issue and adding it to that question would unnecessarily increase its length.
Now I have added one more functionality which is being used quite frequently at many places so I thought creating a separate file would be a nice idea so I created linklayer.c and added linklayer.o to $LIBOBJS.
I added this ...
LIBOBJS= linklayer.o csum.o compact.o protoname.o headers.o
parseargs.o cryptomod.o crc32.o
and this
linklayer.o: linklayer.c
$(CC) -o $# -c -I. $(CFLAGS) $+
I have declared function in sendip_module.h which is already declared and accessed in each of the module present in the project.
But now this multiple definition error is coming ... Have I done something wrong or misunderstood something?
Note: "ipv6_opts" is defined in ipv6.h
$ make all
for subdir in mec ; do \
cd $subdir ;\
make ;\
cd .. ;\
done
make[1]: Entering directory `/home/udit/Desktop/sendip-2.5-mec-2/mec'
make[1]: Nothing to be done for `all'.
make[1]: Leaving directory `/home/udit/Desktop/sendip-2.5-mec-2/mec'
gcc-4.4 -o ipv6.so -fPIC -fsigned-char -pipe -Wall -Wpointer-arith
-Wwrite-strings -Wstrict-prototypes -Wnested-externs -Winline -Werror
-g -Wcast-align -DSENDIP_LIBS=\"/usr/local/lib/sendip\" -shared ipv6.c
libsendipaux.a libsendipaux.a
libsendipaux.a(linklayer.o):(.data.rel.local+0x0)
: multiple definition of `ipv6_opts'
/tmp/ccxa4tMX.o:(.data.rel.local+0x0): first defined here
collect2: ld returned 1 exit status
make: *** [ipv6.so] Error 1
and why this libsendipaux.a libsendipaux.a two times ? Is there something wrong with the Makefile itself.
Do I first need to manually compile it and then add it to libsendipaux.a ?
I am new to this Makefile stuff, so please help me understand how this is all working out here ?
Thanks.
Edit :
Remake debugging output -
remake -x
Reading makefiles...
Updating goal targets....
/home/udit/Desktop/sendip-2.5-mec-2/Makefile:33 File `all' does not exist.
/home/udit/Desktop/sendip-2.5-mec-2/Makefile:48 File `subdirs' does not exist.
/home/udit/Desktop/sendip-2.5-mec-2/Makefile:48 Must remake target `subdirs'.
for subdir in mec ; do \
cd $subdir ;\
make ;\
cd .. ;\
done
make[1]: Entering directory `/home/udit/Desktop/sendip-2.5-mec-2/mec'
make[1]: Nothing to be done for `all'.
make[1]: Leaving directory `/home/udit/Desktop/sendip-2.5-mec-2/mec'
/home/udit/Desktop/sendip-2.5-mec-2/Makefile:48 Successfully remade target file
`subdirs'.
File `ipv6.so' does not exist.
Must remake target `ipv6.so'.
gcc-4.4 -o ipv6.so -fPIC -fsigned-char -pipe -Wall -Wpointer-arith
-Wwrite-strings -Wstrict-prototypes -Wnested-externs -Winline -Werror
-g -Wcast-align -DSENDIP_LIBS=\"/usr/local/lib/sendip\" -shared ipv6.c
libsendipaux.a libsendipaux.a
libsendipaux.a(linklayer.o):(.data.rel.local+0x0)
: multiple definition of `ipv6_opts'
/tmp/ccb0oaXR.o:(.data.rel.local+0x0): first defined here
collect2: ld returned 1 exit status
remake: *** [ipv6.so] Error 1
#0 ipv6.so at ??
#1 all at /home/udit/Desktop/sendip-2.5-mec-2/Makefile:33
33rd line -> all: $(LIBS) subdirs sendip $(PROTOS) sendip.1 sendip.spec
I guess it could not help me out .... actual problem is with my understanding of scenario itself. Please help me bring out of the mess.
the problem you are facing, is that you are linking together several objects where at least two of them define de function ipv6_opts.
since there are two implementations of the function, your linker cannot decide which one to use and throws an error.
the problem most likely comes from the fact that you are linking libsendipaux.a twice into your final binary.
the reason why this happens is here:
%.so: %.c $(LIBS)
$(CC) -o $# $(CFLAGS) $(LIBCFLAGS) $+ $(LIBS)
in this target, $+ will expand to all the dependencies of your target (that is: %.c $(LIBS), which will in turn be resolved to ipv4.c libsendipaux.a
the actual call to the compiler can then be read as $(CC) -o $# $(CFLAGS) $(LIBCFLAGS) ipv4.c $(LIBS) $(LIBS), and $(LIBS) $(LIBS) will expand to libsendipaux.a libsendipaux.a, which will produce the erroneous double linkeage.
so the solution is to remove extraneous $(LIBS) from the .so target:
%.so: %.c $(LIBS)
$(CC) -o $# $(CFLAGS) $(LIBCFLAGS) $+
btw, the errors you get in remake about non-existing files, are because all and subdirs are indeed no files, but phony targets (targets that do no generate files called after the target-name).
to prevent those warnings, add something like the following to your makefile:
.PHONY: all subdirs
Related
I'm trying to write my own makefile for a paho.mqtt project on a Raspberry Pi 4.
I've downloaded & tested the paho.mqtt install and its all working as expected.
So I'm now testing some C code but I just cant figure out the makefile (I'm new to this), my file so far,
NAME = mqtt_test
OBJ = $(NAME).o
LIBS = -libpaho-mqtt3c -libpaho-mqtt3cs
CFLAGS = -Wall -I/usr/local/include -L/usr/local/lib
CC = gcc
EXTENSION = .c
all: $(NAME)
%.o: %$(EXTENSION) $(DEPS)
$(CC) -c -o $# $< $(CFLAGS)
$(NAME): $(OBJ)
$(CC) -o $# $^ $(CFLAGS) $(LIBS)
.PHONY: clean
clean:
#rm -f *.o *~ core $(NAME)
This returns,
gcc -o mqtt_test mqtt_test.o -Wall -I/usr/local/include -L/usr/local/lib -libpaho-mqtt3c -libpaho-mqtt3cs
/usr/bin/ld: cannot find -libpaho-mqtt3c
/usr/bin/ld: cannot find -libpaho-mqtt3cs
collect2: error: ld returned 1 exit status
make: *** [makefile:14: mqtt_test] Error 1
I've checked & the includes and libraries are in the directories I put after the-I and -L flags.
When I look in /usr/bin there is no ld but there are paho files prefixed with paho_ but no library files.
What am I missing?
You don't use -libpaho-mqtt3c (etc.)
The option is -l so when you write -libpaho-mqtt3c the linker is looking for libraries named ibpaho-mqtt3c which of course do not exist: that would be either libibpaho-mqtt3c.a or libibpaho-mqtt3c.so.
You want to use -lpaho-mqtt3c: remove the lib at the front and the extension .a or .so, and add in the option -l.
So I have been searching and looking for something that could help me with the Makefile, but I did not find anything, so thats why I am here.
My makefile right now is like this:
CC = gcc
CFLAGS = -Wall
LDFLAGS += -L$(LIBB)
LDFLAGS += -static lib1.h
LDLIBS = -lm -lpthread -lrt -l
SOURCES=lib1.c prac3.c prac3_reader.c
LIBRARIES=lib1.o
INCLUDES=lib1.h
PROGRAMS=prac3 prac3_reader
all: $(OBJS) $(PROGRAMS)
$(PROGRAMS): $(LIBRARIES) $(INCLUDES)
$(CC) $(LDFLAGS) $(LIBRARIES) $(LDLIBS) $#.o -o $#
%.o: %.c $(INCLUDES)
$(CC) $(CFLAGS) -o $# -c $<
clean:
rm -rf *.o *~ $(PROGRAMS)
I know there are probably a lot of things that can be removed, but I do not really know which ones are. I have two programs called
prac3.c
and
prac3_reader.c
Also, I have my own library called
lib1.c
and also compiled like
lib1.h
When I go to my directory with the terminal and use the command make I recive this error:
gcc -L -static lib1.h lib1.o -lm -lpthread -lrt -l prac3.o -o prac3
/usr/bin/ld: no se puede encontrar -lprac3.o
collect2: error: ld returned 1 exit status
Makefile:15: recipe for target 'prac3' failed
make: *** [prac3] Error 1
I am running on Ubuntu.
The -l flag expects an argument. When it is combined in the gcc statement it causes the prac3.o argument to be considered as the name of a library. There is no such library prac3.o, so you get the error.
In general .o files aren't "libraries". They are object files. Remove the -l flag and you will be fine.
"libraries" are generally .a or .so files from a library path - but even then, you wouldn't specify the suffix (.e.g "-lpthreads").
I am having some confusion about how the '$<' and '$#' macros can be used with a list of elements. My ultimate goal is to compile a directory of C source files into executables with the same name, no extensions. Also I do not want to make object files.
Here is a simple makefile which I would like to upgrade using the macros.
CC = gcc -ansi -std=c99
CCFLAGS = -Wall -pedantic -O3
all : progA progB progC
progA : progA.c
$(CC) $(CCFLAGS) $< -o $#
progB : progB.c
$(CC) $(CCFLAGS) $< -o $#
progC : progC.c
$(CC) $(CCFLAGS) $< -o $#
This works fine, but I don't like the redundancy of the commands. I have found a workaround that works, and a near solution, but was hoping there might be a clear option.
workaround:
CC = gcc -ansi -std=c99
CCFLAGS = -Wall -pedantic -O3
PRGS := $(patsubst %.c,%,$(wildcard *.c))
all :
make $(PRGS)
% : *.c
$(CC) $(CCFLAGS) $#.c -o $#
What I don't like here is the call to make within the command. Running 'make' delivers a message in my terminal that looks something like this:
make[1]: Entering directory '/path/to/dir'
...actual commands...
make[1]: Leaving directory '/path/to/dir'
I am assuming this has to do with opening the same makefile and the [1] refers to the second file descriptor in the open file table (or something along those lines).
near solution:
CC = gcc -ansi -std=c99
CCFLAGS = -Wall -pedantic -O3
SRCS := $(wildcard *.c)
PRGS := $(patsubst %.c,%,$(SRCS))
all : $(PRGS)
$(PRGS) : $(SRCS)
$(CC) $(CCFLAGS) $< -o $#
This almost works, except it is always grabbing the first dependancy!
..... progA.c -o progA
..... progA.c -o progB
..... progA.c -o progC
So, does anyone have a cleaner method to my 'workaround' or perhaps a solution to my 'near solution'? Is there anyway to match the nth target to the nth dependency when running the command?
Thanks!
The $(PRGS): $(SRCS) change is just incorrect. It lists every source file as the prerequisites of every target.
You want to set the prerequisites of the all target to be every program you want built by default. To do that you want to use all: $(PRGS). Not a recipe of calling make again like you had originally.
(If you did want to keep the manual recursive call to make you could use make --no-print-directory on that call to avoid the message but that is still the wrong approach (and if you were going to do that you'd want to use $(MAKE) to handle arguments to the original make correctly.)
A second problem with your original makefile is the use of *.c in the prerequisite list of the % target. That sets the prerequisites of every target to be every *.c file in the directory. That's not what you want. You want each target to have its own .c file as its prerequisite.
You want:
all: $(PRGS)
%: %.c
$(CC) $(CCFLAGS) $#.c -o $#
That being said make has a built-in rule for exactly that foo.c -> foo compilation so you should just use that. That rule uses the $(CC) and $(CFLAGS) variables. So just set those to what you want and you are done.
So this makefile should do what you want. (Note how I moved some arguments to CFLAGS instead of CC. CC should generally, to my knowledge, by the compiler itself and not any arguments.)
CC = gcc
CFLAGS = -ansi -std=c99 -Wall -pedantic -O3
PRGS := $(patsubst %.c,%,$(wildcard *.c))
all : $(PRGS)
I am trying to use the following in a makefile, but when I type make filter_test it gives me the error below, and I can not figure out why. Note the spaces where the input files should be.
CXX=g++
CXXFLAGS=-O1 -pedantic -Wall -Werror -g
DEPS=p2.o recursive.o $#.cpp
p2.o: p2.cpp ; $(CXXFLAGS) -c p2.cpp
recursive.o: recursive.cpp ; $(CXXFLAGS) -c recursive.cpp
filter_test: p2.o $#.cpp recursive.o ; $(CXX) $(CXXFLAGS) recursive.o p2.o $#.cpp -o aaa
Output:
g++ -O1 -pedantic -Wall -Werror -g -o .cpp
g++: fatal error: no input files
compilation terminated.
make: *** [.cpp] Error 4
$# only has a value inside the recipe, so when make sees $# in the prerequisite list, it treats it as an empty string. So make is trying to build the pre-requisite .cpp and using the default rule to build it. To fix this just write:
filter_test: p2.o filter_test.cpp recursive.o
Leave the recipe blank and let make use default rules.
I keep getting this error:
make: *** No rule to make target `all'. Stop.
Even though my make file looks like this:
CC=gcc
CFLAGS=-c -Wall
all: build
build: inputText.o outputText.o main.o
gcc main.o inputText.o outputText.o -o main
main.o: main.c
$(CC) $(CFLAGS) main.c -o main.o
inputText.o: inputText.c
$(CC) $(CFLAGS) inputText.c -o inputText.o
outputText.o: outputText.c
$(CC) $(CFLAGS) outputText.c -o outputText.o
Yes there should be a tab space underneath the target and there is in my make file.
I can get it to work if I try one of the targets like main.o, inputText.o and outputText.o but can't with either build or all.
EDIT:
I just randomly tried running make and telling it the file using the following command:
make -f make
This works but why doesn't just typing make work?
Your makefile should ideally be named makefile, not make. Note that you can call your makefile anything you like, but as you found, you then need the -f option with make to specify the name of the makefile. Using the default name of makefile just makes life easier.