this is my project tree structure:
srcdir/Makefile_parent.make
srcdir/src/Makefile_src.make
srcdir/data/Makefile_data.make
srcdir/other/Makefile_other.make
My question is how to pass from my "Makefile_parent.make" a value readable in the child makefiles..I have:
Makefile_parent.make
ParentData = foo
SUBDIRS = src data other
and later, I want to read it from the other makefiles, for example:
Makefile_src.make
GetParentData = $(ParentData)
But is not working is always empty..any ideas?
In your Makefile_src.make, you need to add this line at the top of the file:
include Makefile_parent.make
Then there is a problem of including the same makefile multiple times. A solution for that (similar to #ifndef in header files ;) )
ifndef MAKEFILE_PARENT_MAKE
MAKEFILE_PARENT_MAKE := 1
...
...
...
...
endif
You need to do this for every makefile you think that might be included, and use a different variable name for each of those files.
Related
My makefile has the following section:
SRCS = src/main.c src/sdlshape.c src/sdlevent.c
OBJS = bin/main.o bin/sdlshape.o bin/sdlevent.o
Is there a way I could use a separate variable to substitute the src/ and bin/ folders in these variables?
I am not sure what exactly you are looking for, but maybe you can do something like this
SRC = src
SRCS = $(SRC)/main.c $(SRC)/sdlshape.c $(SRC)/sdlevent.c
another approach is to use $(wildcard ... ).
If you are looking for a sample of Makefile where you have different folders for includes, objects, etc., take a look here: http://www.owsiak.org/fortran-and-gnu-make/
I know it's Fortran based, but you can still get the feeling of how to structure it.
The question is:
I have a makefile called A.mk (a general makefile for all projects). Over there, I have added all source files in folder src1 using
Var += $(wildcard src1/*.c)
Then, for a specific application I have a makefile (called B.mk), which includes A.mk in itself. Now, I want to substitute the source file foo1.c from folder src1 with a new one foo2.c from folder src2. How can I do that?
How can I do that if I want to substitute (or even delete) multiple files from Var in B.mk.
Thanks for your help in advance.
Make has a number of string functions, filter-out looks like it would apply here
# All .c files
Var := $(filter-out %.c,$(Var))
# A specific file
Var := $(filter-out src/foo.c,$(Var))
I am building a set of Linux kernel modules using shared source code. From what I understand, the Makefile has to be named "Makefile" so I have to use the same Makefile to build two different modules. How can I build two different modules, within the same Makefile, with the same source code, but with two different build options?
For example, my modules are called module1 and module2. So I have the following line to define them:
obj-m := module1.o module2.o
Among other files, both module1 and module2 need to use the same source file code.c, but built with different build options. So say for example, the Makefile contains the following lines:
module1-objs = module1_code.o other_code.o
module2-objs = module2_code.o other_code.o
I want module1_code.o and module2_code.o to be built from code.c, but with different options. Specifically, I want one module1_code.o with a macro defined -DPREPROCEFFOR_FLAG=1, and module2_code.o built without the macro.
From what I understand, the system of Makefiles used in Linux implicitly infers that for an object file called "code.o", the source file is called "code.c", so how would I achieve this? Is is possible? Is there a better way to do this?
You have a problem here, because you obviously have code.c being compiled differently when -DPREPROCEFFOR_FLAG=1 is defined, but once it's compiled into code.o, make won't care about preprocessor flags or whatever because code.o will be already up to date.
You need a way to build code.c to different object files with different C flags. There's probably a clean way to do this (had no chance with O= for out of tree modules), but here's my innelegant yet effective solution for the moment:
my_modules:
cp code.c code_noflags.c
cp code.c code_withflags.c
make -C $$KDIR M=$$PWD modules
rm code_noflags.c code_withflags.c
# module objects
obj-m := module1.o module2.o
# module1 specifics
module1-y := code_withflags.o
CFLAGS_code_withflags.o := -DPREPROCEFFOR_FLAG=1
# module2 specifics
module2-y := code_noflags.o
Just call:
$ make KDIR=/path/to/kernel
You can verify the preprocessor flag is passed to the source file for the right object with:
$ make KDIR=/path/to/kernel V=1 | grep PREPRO
You could also have two separate directories for each module, if this is possible, and have a symbolic link code.c in each one pointing to the common real code.c. However, this is still hackish and doesn't feel right.
One simple solution is, continuing from your Makefile
obj-m := module1.o module2.o
module1-objs = module1_code.o other_code.o
module2-objs = module2_code.o other_code.o
to add two more source files, module1_code.c and module2_code.c.
Then module1_code.c just looks like:
#define PREPROCEFFOR_FLAG 1
#include "code.c"
and module2_code.c is:
#include "code.c"
Or if you like, change the names in the Makefile and source files so that the second include without a define isn't necessary. Also you could make the two source files nothing but an include and use the CFLAGS_module1_code.o variable to add the -D... option to the compiler if you prefer.
This is similar to what happens in the upstream kernel with arch/x86/boot/video-vesa.c and arch/x86/realmode/rm/video-vesa.c etc., where the realmode file just contains:
#include "../../boot/video-vesa.c"
and the video-vesa.c code ends up getting compiled twice with different compiler flags.
This seems preferable to copying the source files, since you end up with a mess there if you want to use the O=... option to the kernel build to keep a clean source tree and build in a separate object tree.
I would like to tell (g)make to include some common initializations from a separate file knowing the relative location of the included file with respect to the main Makefile.
However in the manuals I cannot find any built-in variable that would, for example, give you the name of the current Makefile.
For example if I want to include the content of a file in the same directory as the current make file, instead of hard-wiring the location of the include:
# MAIN Makefile : ./scripts/make/TaskA.mk
include ./scripts/make/Common.inc
...
I would like to write something like the following assuming that _MAKEFILE_ contains the TaskA.mk location:
# MAIN Makefile : ./scripts/make/TaskA.mk
MAKEFILE_DIR=$(dirname $(_MAKE_FILE_))
include $(MAKEFILE_DIR)/Common.inc
Doesn't the manual give a recipe based on MAKEFILE_LIST?
Basically
this_makefile := $(lastword $(MAKEFILE_LIST))
before any include directives should do the trick.
Look at GNU make - Other Special Variables. MAKEFILE_LIST includes all Makefiles read. So, if you take the first one and extract the directory, you're done.
MAKEFILE_DIR=$(dir $(firstword $(MAKEFILE_LIST)))
include $(MAKEFILE_DIR)Common.inc
i have a small java project i want to build using a makefile, the code is in src/package... /*.java, the bytecode should go to bin/package.../*.class.
My current file looks like this (simplified):
JC = javac
SRCDIR = src
BINDIR = bin
JCFLAGS = -d $(BINDIR)/
CLASSES = $(SRCDIR)/package/class1.java $(SRCDIR)/package/class2.java $(SRCDIR)/package/class3.java
default:
$(JC) $(JCFLAGS) $(CLASSES)
It works and does what it should, but there has to be a more elegant way to do this.
For example, is there a way to apply the path ($(SRCDIR) and the package name) as a prefix to all class filenames, so i do not have to put the path seperately in front of every class?
All classes have to be compiled in one javac-call, as there are circular dependencies in them, so using an own target for each class does not work:
default: $(CLASSES)
%.java:
$(JC) $(JCFLAGS) $(SRCDIR)/$#
Thanks for your help.
From the GNU make manual:
$(addprefix prefix,names...)
The argument names is regarded as a series of names, separated by whitespace; prefix is used as a unit. The value of prefix is prepended to the front of each individual name and the resulting larger names are concatenated with single spaces between them. For example,
$(addprefix src/,foo bar)
produces the result ‘src/foo src/bar’.