The question is:
I have a makefile called A.mk (a general makefile for all projects). Over there, I have added all source files in folder src1 using
Var += $(wildcard src1/*.c)
Then, for a specific application I have a makefile (called B.mk), which includes A.mk in itself. Now, I want to substitute the source file foo1.c from folder src1 with a new one foo2.c from folder src2. How can I do that?
How can I do that if I want to substitute (or even delete) multiple files from Var in B.mk.
Thanks for your help in advance.
Make has a number of string functions, filter-out looks like it would apply here
# All .c files
Var := $(filter-out %.c,$(Var))
# A specific file
Var := $(filter-out src/foo.c,$(Var))
Related
We are using make utility in windows to build our project. The version of make is "GNU Make 3.81". I need to understand how our project is built and so have added additional log lines like below which is working as expected --
$(warning Entering componentsWin32.mak )
Additionally I need to find the current directory and the list of files in that directory, for the first one, this is working--
$(warning Entering componentsWin32.make $(CURDIR))
To print the list of files in a directory I tried this but it did-not work --
$(warning Entering componentsWin32.make $(DIR))
Is it possible using $(SHELL...some command) or any other way? Any pointers to this would be helpful.
The function $(wildcard [path string]) will evaluate to a list of files which are desginated by path string: the path string may be written as a glob, so e.g.
$(wildcard $(CURDIR)/src/*.c)
will evaluate to a list of all C files, given that there is a subdirectory src under your current directory with *.c files in it.
You can even pass an arbitrary number of such path expressions:
$(wildcard $(CURDIR)/src/*.c $(MY_INCLUDE_DIR)/*.h)
Obviously, spaces in path names are not allowed.
My makefile has the following section:
SRCS = src/main.c src/sdlshape.c src/sdlevent.c
OBJS = bin/main.o bin/sdlshape.o bin/sdlevent.o
Is there a way I could use a separate variable to substitute the src/ and bin/ folders in these variables?
I am not sure what exactly you are looking for, but maybe you can do something like this
SRC = src
SRCS = $(SRC)/main.c $(SRC)/sdlshape.c $(SRC)/sdlevent.c
another approach is to use $(wildcard ... ).
If you are looking for a sample of Makefile where you have different folders for includes, objects, etc., take a look here: http://www.owsiak.org/fortran-and-gnu-make/
I know it's Fortran based, but you can still get the feeling of how to structure it.
I have a variable (which typically reflects the target's name) in one of the following two forms (with and without extension)
BUILD_DIR/DIR1/DIR2/DIR3/A
BUILD_DIR/DIR1/DIR2/DIR3/B.ext
For a give variable I would like to add another layer (DIR0) under BUILD_DIR and add/change .ext to .new_ext.
So that the variables above are both transformed into
BUILD_DIR/DIR0/DIR1/DIR2/DIR3/A.new_ext
BUILD_DIR/DIR0/DIR1/DIR2/DIR3/B.new_ext
In other words DIR0 is added right after BUILD_DIR and extension is changed if it was present and added if not.
Having a function in the Makefile that does the job should also be sufficient.
Assuming the paths are in a variable such as...
PATHS := BUILD_DIR/DIR1/DIR2/DIR3/A BUILD_DIR/DIR1/DIR2/DIR3/B.ext
Then try something like...
EXTRA_DIR := DIR0
NEW_EXTENSION := new_ext
PATHS := $(addsuffix .$(NEW_EXTENSION),$(patsubst %.ext,%,$(patsubst BUILD_DIR/%,BUILD_DIR/$(EXTRA_DIR)/%,$(PATHS))))
Here is a solution that seems to be the shortest among presented so far
FUNC = $(patsubst $(2)/%,$(2)/$(DIR0)/%.new_ext,$(1:%.ext=%))
$(call FUNC,$(VARIABLE),$(BUILD_DIR))
I have a simple makefile that I use to build some latex files. The syntax looks like this:
pdf: thesis.tex chapters/a.tex chapters/b.tex chapters/c.tex
latexmk -pdf -pdflatex="pdflatex thesis.tex
open:
open thesis.pdf
The files inside chapters folder can increase further with d.tex, e.tex and may even contain subfolders f\section1.tex, f\section2.tex etc.
I manually add all the requried tex files inside my thesis.tex like this which is not a problem.
\input{chapters/a.tex}
\input{chapters/b.tex}
\input{chapters/c.tex}
\input{chapters/d.tex}
\input{chapters/e.tex}
How can I get make target pdf to depend upon any file changes inside chapters and its subdirectories?
How do I write inter task dependency in makefile. If target open depends upon target pdf, how do I write it?
open: pdf will sort-of do what you want for your second question.
Though it would be better to not use the phony pdf target for this.
Instead have a thesis.pdf: target which depends on the right prerequisites and have both pdf: thesis.pdf and open: thesis.pdf targets.
For the first question you can either use something like:
SRCS := $(shell find chapters -name '*.tex')
or use from here:
rwildcard=$(strip $(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2) $(filter $(subst *,%,$2),$d)))
SRCS := $(call rwildcard,chapters,*.tex)
and then:
thesis.pdf: thesis.tex $(SRCS)
to use that variable as the prereq.
If you wanted to get even fancier you could write a script to pull out the actual filenames from the \input{} directives in thesis.tex and use that as your SRCS variable (but that's probably not worth the effort unless you know you will have other, unrelated, .tex files).
I usually use this line OBJECTS = $(SOURCES:.cpp=.o) to substitute the .cpp extension of files in SOURCES to .o extension.
My project now has files with .c extension together with .cpp. How do I modify that line to make it substitute all .c and .cpp extensions to .o?
I would not prefer a two lines solution like below:
OBJECTS_TMP = $(SOURCES:.cpp=.o)
OBJECTS = $(OBJECT_TMP:.c=.o)
I would like something like
OBJECTS = $(SOURCES:(.cpp|.c)=.o)
or even
OBJECTS = $(SOURCES:.*=.o)
Is that possible and how? Thanks!
You can't do it only with the shorthand. You'll have to use the patsubst function:
OBJECTS = $(patsubst %.cpp,%.o,$(patsubst %.c,%.o,$(SOURCES)))
Or you can use one of each:
OBJECTS = $(patsubst %.cpp,%.o,$(SOURCES:.c=.o))
Or, you can do it like this:
OBJECTS = $(addsuffix .o,$(basename $(SOURCES)))