I'm trying to write a simple vhdl code. When I run this code in quartus 2 there is no problem. However, when I run on modelsim, there is an error at line 2, that is error at "use ieee.std_logic_all.1164;" . I have no clue since I'm new to vhdl. By the way, i'm using Modelsim Starter edition 6.5e
library ieee;
use ieee.std_logic_all.1164;
entity tb is
end tb;
architecture behaviour of tb is
component ORG is
port (
a : in std_logic;
b : in std_logic;
c : out std_logic;
);
signal ina, inb, outc : std_logic;
constant period : time := 100ns;
signal done : boolean := false;
begin
process
begin
ina = '0';
inb = '0';
wait for period;
ina = '1';
inb = '0'
wait for period;
done <= true;
wait;
end process;
end behaviour;
You have a number of problems in your code that will cause syntax errors.
As #rene pointed out, the library name is std_logic_1164 - you have "1164" and "all" reversed (the capitalization of IEEE isn't significant).
There should not be a semicolon at the end of the c port line
You should include an end component; statement after the port declaration (that is, after the closing parenthesis and semicolon)
The equals signs in the process should be <=
Finally, there should be a space between 100 and ns
Related
Trying to make a UART Transmitter to send a data from FPGA to PC; 9600 baudrate, 8-bits, no parity, 1 start & stop bit; I wrote a code with VHDL, run synthesis and simulate it in a way I like it to be. I wanted to see it with BASYS 3 FPGA, After created constraints, Run Implementation issued an error in which its called "Opt_Design Error".
library ieee;
use ieee.std_logic_1164.all;
entity rs232_omo is
generic(clk_max:integer:=10400); --for baudrate
port(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
input : in std_logic_vector(7 downto 0);
done : out std_logic;
output : out std_logic;
showstates: out std_logic_vector(3 downto 0)
);
end entity;
architecture dataflow of rs232_omo is
type states is (idle_state,start_state,send_state,stop_state);
signal present_state,next_state : states;
signal data,data_next : std_logic;
begin
process(clk,rst)
variable count : integer range 0 to clk_max;
variable index : integer range 0 to 10;
begin
if rst='1' then
present_state<=idle_state;
count:=0;
data<='1';
done<='0';
elsif rising_edge(clk) then
present_state<=next_state;
count:=count+1;
index:=index+1;
data<=data_next;
end if;
end process;
process(present_state,data,clk,rst,start)
variable count : integer range 0 to clk_max;
variable index : integer range 0 to 10;
begin
done<='0';
data_next<='1';
case present_state is
when idle_state =>
showstates<="1000";
data_next<='1';
if start='1' and rst='0' then
count:=count+1;
if count=clk_max then
next_state<=start_state;
count:=0;
end if;
end if;
when start_state =>
showstates<="0100";
data_next<='0';
count:=count+1;
if count=clk_max then
next_state<=send_state;
count:=0;
end if;
when send_state =>
showstates<="0010";
count:=count+1;
data_next<=input(index);
if count=clk_max then
if index=7 then
index:=0;
next_state<=stop_state;
else
index:=index+1;
end if;
count:=0;
end if;
when stop_state =>
showstates<="0001";
count:=count+1;
if count=clk_max then
next_state<=idle_state;
done<='1';
count:=0;
end if;
end case;
end process;
output<=data;
end architecture;
This's the error message in detail
"[DRC MDRV-1]Multiple Driver Nets:Net done_OBUF has multiple drivers:
done_OBUF_inst_i_1/O,and done_reg/Q"
"[Vivado_Tcl 4-78] Error(s) found during DRC. Opt_Design not run."
What would be the reason for this error?
You are assigning done both in the first and the second process, which is exactly what the implementation is complaining about, you cannot have multiple drivers.
Remove done<='0'; from the first process and it should complete the implementation.
(I didn't check if the rest of the code is doing exactly what you want.)
I'm trying to make a Blink-LED program for a Lattice MachXO3L breakout board. I believe I have the internal-oscillator set up, I just don't know how to connect to its output and make use of it, I get errors when I try. This is on a breakout board which has an LED and a switch. It should oscillate at 1Hz when the switch is flipped one way, and be off when the switch is flipped the other way.
I'e read the PLL usage guide and searched for answers on the internet. I believe I'm close, and just hung up on some syntax issue due to being new to VHDL & FPGAs. Basically, my main code is the 'process and all code below it. Anything above that is basically stuff from the PLL usage guide.
library ieee;
use ieee.std_logic_1164.all;
library machxo3l;
use machxo3l.all;
entity led_blink is
port (
i_switch_1 : in std_logic;
o_led_1 : out std_logic;
i_clock : in std_logic;
osc_int : out std_logic
);
end led_blink;
architecture rtl of led_blink is
COMPONENT OSCH
-- synthesis translate_off
GENERIC (NOM_FREQ: string := "12.09");
-- synthesis translate on
PORT ( STDBY:IN std_logic;
OSC:OUT std_logic);
END COMPONENT;
attribute NOM_FREQ : string;
attribute NOM_FREQ of OSCHinst0 : label is "12.09";
constant C_CNT_1HZ : natural := 6000000;
signal R_CNT_1HZ : natural range 0 to C_CNT_1HZ;
signal R_1HZ : std_logic := '0';
begin
OSCHInst0: OSCH
-- synthesis translate_off
GENERIC MAP(NOM_FREQ => "12.09")
-- synthesis translate on
PORT MAP (STDBY => '0',
OSC => osc_int
);
p_1HZ : process (i_clock) is
begin
if rising_edge(i_clock) then
if R_CNT_1HZ = C_CNT_100HZ-1 then
R_1HZ <= not R_1Hz;
R_CNT_1HZ <= 0;
else
R_CNT_1HZ <= R_CNT_1HZ + 1;
end if;
end if;
end process;
osc_int <= i_clock;
o_led_1 <= R_1HZ when (i_switch_1 = '0') else not R_1HZ;
end rtl;
If I try and assign osc_int to the sensitivity list of the p_1Hz process, I get an error stating that I can not read from an output.
Just a side-note in case other viewers get confused like me, driving i_clock from osc_int appears illogical, because it uses an assignment that seems to suggest the reverse occurs osc_int <= i_clock. Correct me if I'm wrong, but it's assigning an input, to an output, which appears confusing to non-hdl programmers because the direction is decided by the input/output types, rather than the assignment operator itself.
When I do this (link i_clk to osc_int), it saves without giving me errors, it isn't until I try to synthesize the code that it says there are multiple non-tristate drivers for i_clock. The only way I can imagine this being true is if the 'port' from the 'component' section named OSC, being mapped to osc_int, creates two driving signals both linked to i_clock in that single osc_int <= i_clock; statement. But if that's true, how would you access the clock's output at all?
If I just remove the osc_int <= i_clock statement, it works, just with the LED constantly-on/constantly-off, not oscillating/constantly-off.
The clock generated came from inside the OSCH component. Then you don't need any i_clock to achieve what you want. The output of the internal oscillator is the OUT port of the OSCH component.
you can try this :
entity led_blink is
port (
i_switch_1 : in std_logic; -- from the input switch : OK
o_led_1 : out std_logic -- to the blinking led : OK
);
end led_blink;
architecture rtl of led_blink is
COMPONENT OSCH
-- synthesis translate_off
GENERIC (NOM_FREQ: string := "12.09");
-- synthesis translate on
PORT ( STDBY:IN std_logic;
OSC:OUT std_logic);
END COMPONENT;
attribute NOM_FREQ : string;
attribute NOM_FREQ of OSCHinst0 : label is "12.09";
constant C_CNT_1HZ : natural := 6000000;
signal R_CNT_1HZ : natural range 0 to C_CNT_1HZ := 0;
signal R_1HZ : std_logic := '0';
begin
OSCHInst0: OSCH
-- synthesis translate_off
GENERIC MAP(NOM_FREQ => "12.09")
-- synthesis translate on
PORT MAP (STDBY => '0',
OSC => osc_int -- <= this is the 12.09MHz internal clock from the internal oscillator
);
p_1HZ : process (osc_int) is
begin
if rising_edge(osc_int) then
if R_CNT_1HZ = C_CNT_100HZ-1 then
R_1HZ <= not R_1Hz;
R_CNT_1HZ <= 0;
else
R_CNT_1HZ <= R_CNT_1HZ + 1;
end if;
end if;
end process;
o_led_1 <= R_1HZ when (i_switch_1 = '0') else '0';
end rtl;
I am trying to read an image file using textio package in vhdl.
If i open an .jpg with notepad , i will get some junk data but actually it is ASCII data . Here i am trying to read these ascii data and convert them into bytes.
below is my code:
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.std_logic_textio.all;
entity file_io is
port (
clk: in std_logic;
Data: out std_logic_vector(7 downto 0)
);
end entity;
architecture behav of file_io is
signal test_data : std_logic_vector(7 downto 0);
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
begin
File_reader:process(clk)
file f : text open read_mode is "C:\Users\Public\Pictures\Sample Pictures\Chrysanthemum.jpg";
variable L: line;
variable var_int: integer:= 0;
variable var_char: character;
begin
if rising_edge(clk) then
while not endfile(f) loop
readline(f, L);
read(L, var_char);
var_int := character'pos(var_char);
test_data <= std_logic_vector(to_unsigned(var_int, test_data'length));
end loop;
end if;
Data <= test_data;
end process;
end architecture behav;
testbench:
LIBRARY ieee;
use ieee.std_logic_1164.ALL;
use std.textio.all;
ENTITY file_io_test IS
END file_io_test;
ARCHITECTURE behavior OF file_io_test IS
use work.io.all;
signal clk: std_logic := '0';
signal Data: std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
UUT:
entity work.file_io(behav)
port map (
clk => clk,
Data => Data
);
-- Clock process definitions( clock with 50% duty cycle is generated here.
clk_process :process
begin
clk <= '1';
wait for clk_period/2; --for 5 ns signal is '1'.
clk <= '0';
wait for clk_period/2; --for next 5 ns signal is '0'.
end process;
end behavior;
I am getting only one byte in waveform. expected result is : Every clock cycle new character should be rread and new byte should be obtained.
below is waveform:
below is the image I am trying to read:
You have a while loop placed inside the rising_edge part of your process. What happens is that when the first clock edge occurs, the while loop iterates until the end of the file and gives you the last byte of the input image.
Removing the while loop statement should solve your issue.
The question has a fundamental flaw. You can't use textio to read binary values, it's for text.
See IEEE Std 1076-2008 16.4 Package TEXTIO paragraphs 3 (in part) and 4:
Procedures READLINE, WRITELINE, and TEE declared in package TEXTIO read and write entire lines of a file of type TEXT. Procedure READLINE causes the next line to be read from the file and returns as the value of parameter L an access value that designates an object representing that line. If parameter L contains a non-null access value at the start of the call, the procedure may deallocate the object designated by that value. The representation of the line does not contain the representation of the end of the line. ...
The language does not define the representation of the end of a line. An implementation shall allow all possible values of types CHARACTER and STRING to be written to a file. However, as an implementation is permitted to use certain values of types CHARACTER and STRING as line delimiters, it might not be possible to read these values from a TEXT file.
And that can be demonstrated with your Chrysanthemum.jpg:
It is possible in VHDL to read raw characters one at a time (matching your need).
See IEEE Std 1076-2008 5.5 File types:
So all we have to do is declare a file type and we get these procedures defined implicitly.
We can use them to invoke raw read, without any end of line issues caused by textio:
library ieee;
use ieee.std_logic_1164.all;
entity file_io is
port (
clk: in std_logic;
Data: out std_logic_vector(7 downto 0);
done: out boolean
);
end entity;
architecture foo of file_io is
use ieee.numeric_std.all;
begin
File_reader:
process (clk)
-- "C:\Users\Public\Pictures\Sample Pictures\Chrysanthemum.jpg";
constant filename: string := "Chrysanthemum.jpg"; -- local to sim
variable char_val: character;
variable status: FILE_OPEN_STATUS;
variable openfile: boolean; -- FALSE by default
type f is file of character;
file ffile: f;
variable char_count: natural := 0;
begin
if rising_edge (clk) then
if not openfile then
file_open (status, ffile, filename, READ_MODE);
if status /= OPEN_OK then
report "FILE_OPEN_STATUS = " &
FILE_OPEN_STATUS'IMAGE(status)
severity FAILURE;
end if;
report "FILE_OPEN_STATUS = " & FILE_OPEN_STATUS'IMAGE(status);
openfile := TRUE;
else
if not endfile(ffile) then
read(ffile, char_val);
-- report "char_val = " & character'image(char_val);
char_count := char_count + 1;
Data <= std_logic_vector (
to_unsigned(character'pos(char_val),
Data'length) );
end if;
if endfile(ffile) then -- can occur after last character
report "ENDFILE, read " &
integer'image(char_count) & "characters";
done <= TRUE;
FILE_CLOSE(ffile);
end if;
end if;
end if;
end process;
end architecture foo;
library ieee;
use ieee.std_logic_1164.all;
entity file_io_test is
end file_io_test;
architecture behavior of file_io_test is
signal clk: std_logic := '0';
signal data: std_logic_vector(7 downto 0);
signal done: boolean;
constant clk_period: time := 10 ns;
begin
uut:
entity work.file_io(foo)
port map (
clk => clk,
data => data,
done => done
);
clk_process:
process
begin
if not done then
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
else
wait;
end if;
end process;
end architecture behavior;
Now we can have all the characters than can delimit a line show up in our read:
Note that package std.textio is not made visible through any context item.
This has been driving me crazy. Here’s the code I have so far:
signal SYS_CLK : std_logic := '0'; --Input
signal InputSignal : std_logic := '0'; --Input
signal SyncOutputSignal : std_logic; --Output
------------------------------------------------------
stim_proc:process(SYS_CLK)
begin
if (rising_edge(SYS_CLK)) then
if (InputSignal = '1') then
assert (SyncOutputSignal = '0') report "Bad Pulse..." severity ERROR;
end if;
end if;
end process stim_proc;
And a picture of the ISim waveform ---> i.imgur.com/G5KvCQe.jpg
The purpose of this test is to confirm that when on rising_edge(SYS_CLK) if InputSignal = '1', then a pulse is emitted (SyncOutputSignal) equivalent and in line to SYS_CLK's period.
However, an Error report is being issued everytime the CLK goes high and InputSignal is High.
Long story short, I need a way to tell the program to wait for the next InputSignal Pulse before testing the assert statement listed in my code again. Any ideas??
It sounds like you are trying to check for an edge condition on InputSignal. When checking for an edge condition in hardware, there's a simple thing you can do. Create a registered version of InputSignal (I called it Reg_InputSignal). Then change your if statement to check for a 1 on InputSignal and a 0 on Reg_InputSignal. This is a rising edge condition on InputSignal and should only trip the if statement for 1 clock cycle.
architecture RTL of Entity_Name is
signal Reg_InputSignal : std_logic := '0';
begin
stim_proc : process(SYS_CLK)
begin
if (rising_edge(SYS_CLK)) then
Reg_InputSignal <= InputSignal;
if (InputSignal = '1' and Reg_InputSignal = '0') then
assert (SyncOutputSignal = '0') report "Bad Pulse..." severity error;
end if;
end if;
end process stim_proc;
So, I'm making a college project where I have to make the VHDL simulation of 3 counters using Xilinx. One of the counters goes from 5 down to 0, the other goes from 4 down to 0 and the other goes from 13 to 0, but it counts twice with one clock signal. The code I developed was something like these (it was based on a schematic so the entity and architecture is supposed to remain untouched I think):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY projetesquema2_projetesquema2_sch_tb IS
END projetesquema2_projetesquema2_sch_tb;
ARCHITECTURE behavioral OF projetesquema2_projetesquema2_sch_tb IS
COMPONENT projetesquema2
PORT( CLOCK : IN STD_LOGIC;
ACL : IN STD_LOGIC;
CAT : OUT STD_LOGIC;
CRT : OUT STD_LOGIC;
CLT : OUT STD_LOGIC;
ACA : IN STD_LOGIC);
END COMPONENT;
SIGNAL CLOCK : STD_LOGIC;
SIGNAL ACL : STD_LOGIC;
SIGNAL CAT : STD_LOGIC;
SIGNAL CRT : STD_LOGIC;
SIGNAL CLT : STD_LOGIC;
SIGNAL ACA : STD_LOGIC;
BEGIN
UUT: projetesquema2 PORT MAP(
CLOCK => CLOCK,
ACL => ACL,
CAT => CAT,
CRT => CRT,
CLT => CLT,
ACA => ACA
);
*** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then
if (ACA='0') then
CAT <= "0000";
else
CAT <= CAT + 1;
end if;
end if;
end process;
process (CAT)
begin
if (CAT'event and CAT='1') then
CRT <= CRT + 1;
end if;
end if;
end process;
process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then
if (ACL='0') then
CLT <= "0000";
else
CLT <= CLT + 1;
end if;
end if;
end process;
end Behavioral;
WAIT; -- will wait forever
END PROCESS;
*** End Test Bench - User Defined Section ***
END;
This gives me some errors that I don't know how to fix, hope somebody can actually help me.
Errors are:
ERROR:Line 54: Syntax error near "process".
ERROR:Line 55: Syntax error near "begin".
ERROR:Line 58: Type std_logic does not match with a string literal
ERROR:Line 60: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
ERROR:Line 68: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
ERROR:Line 70: Syntax error near "if".
ERROR:Line 77: Type std_logic does not match with a string literal
ERROR:Line 79: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
ERROR:Line 22: Unit ignored due to previous errors.
ERROR:Line 85: Syntax error near "WAIT".
Assuming the asterisk delimited comments aren't part of the VHDL design specification:
You have an extraneous PROCESS and BEGIN:
tb : PROCESS
BEGIN
process (CLOCK)
begin
There's an extra end if:
process (CAT)
begin
if (CAT'event and CAT='1') then
CRT <= CRT + 1;
end if;
end if;
end process;
There are more extraneous statements:
end Behavioral;
WAIT; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
This should simply be:
end Behavioral;
or
end architecture Behavioral;
And now we find semantic errors:
'CAT' is defined as a scalar std_logic:
SIGNAL CAT : STD_LOGIC;
SIGNAL CRT : STD_LOGIC;
SIGNAL CLT : STD_LOGIC;
SIGNAL ACA : STD_LOGIC;
and used in the component declaration for projetesquema2.
You can't promote it to a std_logic_vector value:
CAT <= "0000";
else
CAT <= CAT + 1;
or add an integer to it like it was declared as an unsigned (the use clause references package numeric_std, and BTW the unisim stuff can be dumped).
The same argument hold true for CRT and CLA. projetesquema appears to translate into English as project plan, there is insufficient information to advise an answerer how to fix these issues.
Perhaps if you made the entity and architecture for projetesquema2 available or told us what it does and what the port names mean?
It seems you've either been thrown in the deep end, missed part of your reading list or haven't been paying attention in class from the errors we see so far.
Stackoverflow may not where you should be going as a first resource for learning VHDL, and the Xilinx tools are somewhat unfriendly for error messages.
I know this it's in English but try this reference for an overview of VHDL.
Right around here you start defining a process inside a process, which isn't legal. Nor does it make much sense.
tb : PROCESS
BEGIN
process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then