discrete cosine transform using VHDL - vhdl

Question

Am working on discrete cosine transform using VHDL. Am trying to convert the VHDL code from integer to standard logic vector. I applied some of the techniques i read online and from textbooks but it didn't work. Below is the code i tried converting.I would like the input length to be 8 bit and the output length to be 12bit.Thank you.
entity dct is
port (
Clk : in BIT;
Start : in BIT;
Din : in INTEGER;
Done : out BIT;
Dout : out INTEGER
);
end dct;
architecture behavioral of dct is
begin
process
type RF is array ( 0 to 7, 0 to 7 ) of INTEGER;
variable i, j, k : INTEGER;
variable InBlock : RF;
variable COSBlock : RF;
variable TempBlock : RF;
variable OutBlock : RF;
variable A, B, P, Sum : INTEGER;
begin
Here is the one i tried after reading some books and i keep getting errors.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dct is
port (
Clk : in std_logic;
Start : in std_logic;
Din_temp: in INTEGER;
temp := conv_std_logic_vector(Din_temp, 8);
Done : out std_logic;
Dout_temp: out INTEGER;
temp := conv_std_logic_vector(Dout_temp, 9));
end dct;
architecture behavioral of dct is
begin
process
type RF is matrix( 0 to 7, 0 to 7 ) of ;
variable i, j, k : std_logic_vector(7 downto 0);
variable InBlock : RF;
variable COSBlock : RF;
variable TempBlock : RF;
variable OutBlock : RF;
variable A, B, P, Sum : std_logic_vector(7 downto 0);
begin

Answer 1

seems that you combined the entity declaration with the signal assignement; this doesn't work like this! keep the entity as it was and use the type conversion functions inside your architecture. the example below shows this for Din and Dout:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dct is
port (
Clk : in BIT;
Start : in BIT;
Din : in INTEGER;
Done : out BIT;
Dout : out INTEGER
);
end dct;
architecture behavioral of dct is
signal temp_din: std_logic_vector(7 downto 0);
signal temp_dout: std_logic_vector(11 downto 0);
begin
temp_din<=std_logic_Vector(to_unsigned(Din,8));
Dout<=to_integer(unsigned(temp_dout));
...
of course, you can also use std_logic_vector directly in your entity:
entity dct is
port (
Clk : in BIT;
Start : in BIT;
Din : in std_logic_Vector(7 downto 0);
Done : out BIT;
Dout : out std_logic_vector(11 downto 0)
);
end dct;

Answer 2

Integers are perfectly synthesisable and work just fine as ports, so if the module you have is working satisfactorily, and synthesise correctly, leave it well alone.
It is good practice to use ranged integers : for example, if Din, Dout represent values in the range 0 to 255, create either a new integer type or a subtype for them :
type Int_8 is new Integer range 0 to 255; -- or
subtype Int_8 is Integer range 0 to 255;
(The difference is that subtypes can be freely mixed with other Integers, but accidentally mixing the new type with integer will be flagged by the compiler as an error).
The benefit of this is that synthesis won't try to create 32-bit math units where only 8 (or 3 or 19) bits is needed. Normally it does, then trims the excess bits later so it doesn't cost any more gates, it just floods the report files with "trimming redundant logic" messages...
However I am guessing the problem you have is interfacing this core with other parts of a design, implemented in a less enlightened fashion, which have std_logic_vector ports.
Then you can implement a wrapper to adapt this DCT core to a std_logic_vector environment.
I have used different techniques for different port signals : conversions in the port maps are neater, but some tools have problems (bugs) handling them. So I have used internal signals as adapters for Start and Dout, to show how you can work around such problems.
In reality, pick one or the other!
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity std_lv_dct is
port (
Clk : in std_logic;
Start : in std_logic;
Din : in std_logic_vector(7 downto 0);
Done : out std_logic;
Dout : out std_logic_vector(11 downto 0);
);
end std_lv_dct;
architecture wrapper of std_lv_dct is
Dout_int : integer range 0 to 4095;
Start_int : bit;
begin
-- internal signals as type adapters
Dout <= std_logic_vector(to_unsigned(Dout_int),11);
Start_int <= to_bit(Start);
-- direct entity instantiation for the real core
Transform : entity work.dct
port map(
Clk => to_bit(Clk),
Start => Start_int,
Din => to_integer(unsigned(Din)),
std_logic(Done) => Done,
Dout => Dout_int
);
end architecture wrapper;