using sin and cos through the lookup table in VHDL - vhdl

Question

i'm using the sin/cos lookup table in VHDL known as sincos_lut.vhd and i'm getting an error when used with my code. I'm implementing my datapath and i need to perform sin and cos on an integer value. I do not know where my problem is but here is the code and error:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.MATH_REAL.all;
entity DFT is
port(
clk_en, clk, reset, Clock: std_logic;
t_sel,K_sel,sr_sel,si_sel,ld_t,ld_K,ld_sumreal,ld_sumimag,ld_angle: in std_logic;
N: in integer;
e: in std_logic_vector(3 downto 0);
outreal, outimag: out integer;
sig1, sig2: out std_logic
);
end DFT;
architecture str of DFT is
component Adder
Port( a, b: in integer;
f: out integer
);
end component;
component Reg
Port(
Clk: in std_logic;
ld: in std_logic;
a: in integer;
f: out integer
);
end component;
component Mul
Port(
a, b: in integer;
f: out integer
);
end component;
component LT
Port(
a, b: in integer;
sig: out std_logic
);
end component;
component Div
Port(
a, b: in integer;
f: out integer
);
end component;
component Mux
Port(
sel: in std_logic;
a, b: in integer;
f: out integer
);
end component;
component Mem
port( Clock: in std_logic;
Read: in std_logic;
Write: in std_logic;
Address: in integer;
Data_in: in integer;
Data_out: out integer
);
end component;
component sincos_lut Port
(
reset : in std_logic;
clk : in std_logic;
clk_en : in std_logic;
theta : in integer;
sin_data : out signed(integer);
cos_data : out signed(integer)
);
end component;
signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23,s24,s25,s26,s30,s31,s32,s33 : integer;
constant MATH_PI : real := 3.14159_26535_89793_23846;
begin
G1: Mux port map(K_sel,0,s1,s2);
G2: Mux port map(t_sel,0,s3,s4);
G3: Reg port map(Clk,ld_K,s2,s5);
G4: Reg port map(Clk,ld_t,s4,s6);
G5: LT port map(s5,N,sig1);
G6: LT port map(s6,N,sig2);
G7: Adder port map(s5,1,s1);
G8: Adder port map(s6,1,s3);
G9: Div port map(s5,N,s7);
G10: Mul port map(s7,s6,s8);
G11: Mul port map(s8,integer(MATH_PI),s9);
G12: Mul port map(s9,2,s10);
G13: Reg port map(Clk, ld_angle,s10,s11);
G14: Mem port map(Clock,'1','0',s6,0,s12);
G15: Mem port map(Clock,'1','0',s6,0,s13);
G16: Mul port map(s12,s33,s14);
G17: Mul port map(s13,s30,s15);
G18: Adder port map(s14,s15,s16);
G19: Mux port map(sr_sel,0,s17,s18);
G20: Reg port map(Clk, ld_sumreal,s18,s19);
G21: Adder port map(s16,s19,s17);
G22: Mul port map(s12, -1,s20);
G31: sincos_lut port map(reset, clk, clk_en, s11, s30, s31);
G32: sincos_lut port map(reset, clk, clk_en, s11, s32, s33);
G23: Mul port map(s20, s30, s21);
G24: Mul port map(s13, s33, s22);
G25: Adder port map(s21, s22,s23);
G26: Mux port map(si_sel,0,s24,s25);
G27: Reg port map(Clk, ld_sumimag,s25,s26);
G28: Adder port map(s23,s26,s24);
G29: Mem port map(Clock, '0','1',s5,outimag);
G30: Mem port map(Clk, '0','1',s5,outreal);
sincos_lut
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sincos_lut is
port
(
reset : in std_logic;
clk : in std_logic;
clk_en : in std_logic;
theta : in integer;
sin_data : out signed(integer);
cos_data : out signed(integer)
);
end sincos_lut;
architecture rtl of sincos_lut is
signal theta_int : integer range 0 to 4095 := 0;
signal sin_data_int : signed(integer);
signal cos_data_int : signed(integer);
begin
theta_int <= theta;
process(reset,clk)
begin
if(reset = '1')then
sin_data_int <= to_signed(0,12);
cos_data_int <= to_signed(0,12);
elsif(rising_edge(clk)) then
if clk_en = '1' then
sin_data <= sin_data_int;
cos_data <= cos_data_int;
case theta_int is
end str;
Errors:
Error (10476): VHDL error at DFT.vhd(119): type of identifier "s30" does not agree with its usage as "SIGNED" type
Error (10558): VHDL error at DFT.vhd(119): cannot associate formal port "sin_data" of mode "out" with an expression
Error (10476): VHDL error at DFT.vhd(119): type of identifier "s31" does not agree with its usage as "SIGNED" type
Error (10558): VHDL error at DFT.vhd(119): cannot associate formal port "cos_data" of mode "out" with an expression
Line 119 is:
G31: sincos_lut port map(reset, clk, clk_en, s11, s30, s31);

Answer 1

Your errors are because s30 and s31 are integers and you are connecting them to a signed ports.
Kevin.

Answer 2

type of identifier "s30" does not agree with its usage as "SIGNED" type
This error is caused by mixing different types. The type of s30 is integer, but you are trying to map it to a port of type signed.
cannot associate formal port "sin_data" of mode "out" with an expression
This error is normally caused by "reading" an output port in your logic, but I don't see a clear reason for this error. Possibly this is related to your ports of type : signed(integer). Signed() is used for type conversion.

Answer 3

Your code isn't a Minimal, Complete, and Verifiable example. Note your sincos_lut doesn't analyze either.
signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23,s24,s25,s26,s30,s31,s32,s33 : integer;
constant MATH_PI : real := 3.14159_26535_89793_23846;
signal signed_s30: signed (11 downto 0);
signal signed_s31: signed (11 downto 0);
signal signed_s32: signed (11 downto 0);
signal signed_s33: signed (11 downto 0);
begin
s30 <= to_integer(signed_s30);
s31 <= to_integer(signed_s31);
s32 <= to_integer(signed_s32);
s33 <= to_integer(signed_s33);
You can create signed versions of s30, s31, s32 and s33 and convert
and assign them to s30, s31, s32, s33.
Also note there were associated errors in the sincos_lut, both in port declarations and signal declarations. A type name doesn't represent a range constraint. These have been fixed by:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sincos_lut is
port
(
reset : in std_logic;
clk : in std_logic;
clk_en : in std_logic;
theta : in integer;
sin_data : out signed(11 downto 0); -- integer);
cos_data : out signed(11 downto 0) -- integer)
);
end sincos_lut;
architecture rtl of sincos_lut is
signal theta_int : integer range 0 to 4095 := 0;
signal sin_data_int : signed(11 downto 0); -- integer);
signal cos_data_int : signed(11 downto 0); -- integer);
The range of the signed values (actually the length) is determined by the to_signed function calls in the process.
Note use package numeric_std function to_integer, and in dft:
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.std_logic_arith.all;
-- use ieee.std_logic_unsigned.all;
-- use ieee.math_real.all;
use ieee.numeric_std.all; -- never, never mix std_logic_arith/numeric_std
-- (see sincos_lut)
Type declarations in two different packages are unique regardless of whether they have the same name and base type or not. They are not compatible. If your tool let's you it is not compliant to the VHDL standard.
G31: sincos_lut port map(reset, clk, clk_en, s11, signed_s30, signed_s31);
G32: sincos_lut port map(reset, clk, clk_en, s11, signed_s32, signed_s33);
That lops of those errors, but reveals two more:
G29: Mem port map(Clock, '0','1',s5,outimag);
G30: Mem port map(Clk, '0','1',s5,outreal);
If you look at your mem component and the positional association list in the instance port maps you'll find you're missing an integer argument for both of these representing Address.
I don't think you've revealed enough of your 'precious' IP from someone to tell what should be connected here. It's part of the price in seeking help, showing what you got. When someone tells you it isn't a minimum example, in this case it would be throwing out component instantiations and signals not connected to the actual error reports.
Also note the promiscuous use of unconstrained integers which can end up implying 32 bit values in synthesis. You should be careful and constrain everything you can.
For instance defining the range constraint for the integer address going to the Mem component defines how big the memory is.
Dummy-ing up a signal Address, an integer and inserting it in the component allows dft to finish analyzing:
G29: Mem port map(Clock, '0','1',Address,s5,outimag);
G30: Mem port map(Clk, '0','1',Address,s5,outreal);
It's not possible to elaborate your design without dummy-ing up entity and architecture pairs for all your instantiated components or eliminating them (which would lead you to a second question later).
(And you could have produced integers from the sincos_lut entity/architecture pair, but without a range constraint that would have likely been a 32 bit value).