I'm encountering the need to run a script after configure is done, automatically.
That is, when I run ./configure I would like it to end up by running ./script.sh, and it must be the last thing the configure runs.
Is there any way to do this?
Thanks
You can put any arbitrary shell code in your configure.ac. Since AC_OUTPUT should be the last line of your configure.ac, anything after it will be run after config.status is run.
To make hello-world.sh execute after config.status, just append it to your configure.ac:
AC_CONFIG_FILES([Makefile])
AC_OUTPUT
$srcdir/hello.sh
$srcdir is required if building out of the srcdir.
Related
Suppose I had a python project that uses make to install. I want to be able to run the project without installing it first. So I created this make rule:
run:
#echo "Running projectname"
#PYTHONPATH=${PYTHONPATH}:$(abs_srcdir)/..; ./projectname
Where ./projectname runs a simple python script that sets up and runs the project, but that's not important here. Like that, I can simply execute make run in the root folder of the project to execute and test my application, which works perfectly fine. Now, I want to pass some command line arguments to the program. I tried make run --help, which just printed make's help text. Running make run -- --help printed
Running projectname
make: *** No rule to make target '--help'. Stop.
The application is run, and after I exit it, make tries to execute a target --help.
Now, how can I pass for example a --help argument to my application through make ?
make run ARGS=“arg1 arg2”
$(ARGS) in your makefiles would be expanded to what you have passed.
I am looking for a way to get CMake to re-run a shell command every time it detects that the dependencies for a specific target/executable has changed. I tried adding a custom command the has a dependency on a target, but this does not seem to be doing the trick.
Example of what I thought might work:
ADD_CUSTOM_COMMAND(
OUTPUT temp
DEPENDS my_Target
COMMAND ./some_command.sh)
Any suggestions of a command that may be able to run a command when a dependency change has been detected for a target. Or even better if we can check for a change in specific files.
From your description, it sounds like you might want this:
cmake_minimum_required(VERSION 2.8)
project(cmaketest)
add_custom_command(OUTPUT some_file.cpp
DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/bar.cpp
COMMAND ${CMAKE_COMMAND} -E copy
${CMAKE_CURRENT_SOURCE_DIR}/bar.cpp
${CMAKE_CURRENT_BINARY_DIR}/some_file.cpp
VERBATIM
)
add_executable(mn main.cpp some_file.cpp)
Put the output file in the source list of the target which depends on it.
add_custom_command() uses simple check for OUTPUT file existence to determine if the command should be run. If it doesn't exist, then CMake do make my_Target and only then run your command. At the same time, if OUTPUT exist, CMake doesn't run anything at all.
To achieve what you want you need to add_custom_target() (probably with ALL keyword to run it with make) and implement checking for changes inside your some_command.sh.
Say I have a makefile, upon compiling with the command make, it produces an executable named 'run'.
So far, I know that 'make' is used to compile multiple source codes but what I have never heard of is you can use 'make' to execute the executable.
Is it possible to execute the binary with this command later with 'make run'?
I think this one is basic question but I'm yet to find an answer.
Sorry if it hurts some of the people here. =D
You can create a .PHONY target called run.
.PHONY: run
run:
./executableName
.PHONY means that the makefile won't create a file and will run the command every time.
Note: Most likely you have a target that is to make the executable. Do not give the .PHONY target the same name as the executable.
No, to run the program type
./run
I am absolutely new in gfortran+minGW.
I need to create makefile.
When I run
$ gfortran -c q.f
All is ok!
But how can I run makefile like this?
CC = gfortran
q.o : q.f
$(CC) -c q2.o q2.f
I receive error “CC: command not found”.
(OS – Win 7 (64))
Tanks!!!
It kind of looks like you're trying to run the makefile as a regular script. Try
$ make
or
$ make -f mymakefilename
if you named the file something other than "makefile" or "Makefile".
You can potentially just execute the makefile, but if so you need a "shebang" line, something like
#!/usr/bin/make
at the top of the file, but frankly hardly anyone uses that option. Just use the make(1) command.
Update
It's because they're in the wrong order. Makefiles process (by default) the first target in the file. When you run make it sees the rule to make, q.o from q.f, it compiles it, and says, "Okay, I'm done."
If you put the q.exe target first, it says "Hmmm, I want to build q.exe and to do that I need a q.o. Do I have a q.o? No? Okay, hen I'll build a q.o. I have a rule for that -- I can build a q.o from q.f. okay, that's done. Now can I build q.exe? Oh, yes, I can. I'll build q.exe. Anything? Nope, I'm done."
If you were to use the commend
$ make q.exe
then you'd explicitly tell make to make q.exe, which would cause the same thing to happen, but better you should reorder your makefile and get used to the way they work.
Is there a way to have make echo commands that are manually suppressed with # in the makefile? I can't find this in the help or man page, it just says "--quiet" to do the opposite.
The most obvious idea is to change the shell that runs the commands, e.g. modify your makefile and add to the top SHELL = sh -xv.
Another solution is to change how you call make to make SHELL='sh -xv'
Lastly if your Makefile is generated by cmake then call make with make VERBOSE=1
I run into this question from time to time using cmake because it hides the command. You can use "make VERBOSE=true" to get them to print out.